Content originally posted in LPCWare by IanB on Fri Apr 17 03:18:29 MST 2015
Sorry, I was too vague.
What I meant to ask is for a circuit diagram of the internal protection circuitry on a GPIO pin.
These devices are 5V tolerant, so they don't have the same protection circuitry as your bog-standard CMOS, because there is no diode to Vdd. I was wondering what was there to prevent damage from positive-going spikes. Is there a zener?
Not all the family is the same as LPC11xx is 5V tolerant, and LPC12xx isn't, and it has diodes from input to Vdd.
