LPC55S69: Need clarification on I2S clocking

[scottm]

I'm setting up a FlexComm module for I2S operation on an LPC55SS69 and I'm finding the documentation to be very scattered and kind of inconsistent. I think I've got it, but I could use some input here to make sure I've got this right.

I need to set the baud rate to 2.4 MHz. The main clock is running at 150 MHz from PLL0 with a 16 MHz crystal. The accuracy of the 96 MHz FRO isn't good enough for this application, and honestly it seems pretty loose for any audio application but it's the only one shown in the demo projects.

The I2S section of the user's manual points us to table 79, where "system PLL divided clock" is an option. This took me a bit to find because the SDK calls it PLL0_DIV but that isn't used in the manual. Instead figure 4 shows that it's pll0_clk_div, and the register is called PLL0DIV.

Except it's not, which made it impossible to search for. Turns out it's actually called PLL0CLKDIV in 4.5.59, but no information is given on its use. Incidentally the clocks configuration tool calls it PLL0DIV (like the SDK but not the manual text) and calls the output pll0_clk_div (like the manual text but not the SDK).

So I'm hoping that pll0_clk_div is only used by FlexComm modules, but there's nothing I can see that guarantees that.

In the clocks tool, FRGCTRL0_MUL is fixed at 256 and FRGCTRL0_DIV is configurable. In the manual, they're listed under FLEXFRG0CTRL:DIV and FLEXFRG0CTRL:MULT (again, impossible to search because of the name mismatch) and it's DIV that's fixed at 256.

The SDK documentation is worse than useless here. The only relevant function is I2S_SetBitClockRate, which doesn't have any description in the SDK reference and in the code only says "Transmitter bit clock rate configurations". You might think it'd set the bit clock rate, and it certainly says nothing about its limitations, but all it actually does is a bit of trivial math on word size and sample rate to set the integer divider. If I just blindly give it the values it's looking for, it'll return a completely unusable result with no indication that it couldn't do what was asked of it.

To understand what the function does, you have to read the whole function, then go to the datasheet to find out what the register does, and then go figure out how to actually do what the function name suggests it does. This is what I mean by worse than useless - if it wasn't there at all, you'd be doing all of the same work anyway except for the part where you have to read the SDK function.

So what I've got now is a 150 MHz output from PLL0 being divided by 4 to get 37.5 MHz at pll0_clk_div, FCCLKSEL0 set to select that clock as input to the FRG, the FRG set to 400/256 to yield 24 MHz for FXCOMCLK0 while keeping it under the 25 MHz limit, and DIV is set to 10 to divide it to 2.4 MHz.

Is this correct? And is the pll0_clk_div signal used for anything other than FlexComm modules?

Thanks,

Scott

[xiangjun_rong]

Hi, Scott,

Pls refer to the following pic in section 4.4.1 Clock generation in UM11126.pdf

The FCLKx is the only driving clock of FlexComm module, the FRGx can be a divider ranging from 1 to 2(for example the divider can be 1, 1.1, 1.2...). For detailed inf, pls refer to section 4.5.49 Fractional rate divider for each Flexcomm Interface frequency.

So this is the I2S clock divider link you are using

PLL0_clk--------->PLL0_CLK_DIV------------>FCLKx------------>I2S bit clock

1)From PLL0 clock to PLL0_CLK_DIV clock, you can set PLL0 clock divider reg, which ranges from 1 to 256. For detailed inf, pls refer to section 4.5.59 PLL0 clock divider in UM11126.pdf

4.5.59 PLL0 clock divider
This register determines the divider value for the PLL0 output, if used by the application

2)From PLL0_CLK_DIV to FCLKx, here x represents the FlexComm module index, pls refer to 4.5.49 Fractional rate divider for each Flexcomm Interface frequency, you can write the FLEXFRG0CTRL to set the fractional clock divider from 1 to 2.

3)From FCLKx to I2S bit clock, pls refer to 37.7.4 Clock divider register, you can write the Clock divider register (DIV, offset = 0xC1C) to set up the divider, the divider range is from 1 to 4096

with above setting, I suppose you can get the required I2S bit clock

Hope it can help you

BR

XiangJun Rong

[scottm]

Can you confirm that pll0_clk_div is only used by FlexComm modules? I've got the baud rate I need, I just want to make sure I'm not going to be causing problems for myself elsewhere by changing the divider there.

Thanks,

Scott

[xiangjun_rong]

Hi,

From the UM11126.pdf, I suppose that the pll0_clk_div clock is only used by FlexComm modules, it is not used by the other modules.

Hope it can help you

BR

XiangJun Rong