LPC5514 I2S SLAVE

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LPC5514 I2S SLAVE

779件の閲覧回数
qingyunliu
Contributor II

LPC55S69 A I2S SLAVE --> LPC55S69 B I2S MASTER

LPC55S69 B as I2S master , provide MCLK. LRCK, BCLK to LPC55S69 A I2S SLAVE.

LPC55S69 A as I2S slave,  provide audio data to LPC55S69 B I2S MASTER

how can I refer to which demo? 

IF I2S slave want transmit audio data ,should put data to TXFIFO or RXFIFO?

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

From your description, I see that you want to use two LPC5569-EVK boards to implement the I2S communication.

 

In the SDK package, there is I2S master example

xiangjun_rong_0-1687757856732.png

 

For the I2S slave, you can develop the slave I2S example based on the master example.

static i2s_config_t s_RxConfig;

I2S_TxGetDefaultConfig(&s_RxConfig);
s_TxConfig.divider = DEMO_I2S_CLOCK_DIVIDER;
s_TxConfig.masterSlave = kI2S_MasterSlaveNormalSlave; //DEMO_I2S_TX_MODE;
I2S_TxInit(I2S6, &s_RxConfig);

In the slave mode, the SCK and WS for I2S6 will be input pins, you can assign the I2S6 pin in the pin_mux.c

Hope it can help you

BR

XiangJun Rong

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740件の閲覧回数
qingyunliu
Contributor II
thanks for reply.
Can LPC support config I2S bitdepth?
I saw SDK support set I2S datelen and framelen only.
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729件の閲覧回数
xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

what do you mean for the " I2S bitdepth"? do you mean that the WS occupies only one SCK cycle instead of 50% duty cycle? if it is the case, of course, it supports the WS occupies only one clock cycle of SCK.

As the following Fig, the WS width is controlled by MODE bits.

Hope it can help you

BR

XiangJun Rong

 

xiangjun_rong_0-1687918535548.png

 

Hope it can help you

BR

XiangJun Rong

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