LPC546xx Audio PLL driver issue

[stefanburstrom]

Hi!

I just noticed that the CLOCK_SetAudioPLLFreq seems wrong in the SDK. (I just downloaded the 2.8.2 SDK to be sure)
This code seem to inherent the system pll acceleration code. Which means that when I turn on the audio pll my system crashes as the pll is set to an insanely high value. I'd like to be able to modify the audio pll values while the system is still running at 180 MHz.

Is there a similar acceleration implementation for the audio pll or should I just comment out the part where SYSCON->SYSPLLMDEC is modified?

Best regards,

Stefan

[Alice_Yang]

Hello Stefan,

In the description of this function, it will not alter any source clocks (ie main system clock),

you can first try to use it, if have some problem, tell us.

Regards,

Alice

[stefanburstrom]

I know what the function is supposed to do, but the implementation does not match: Check the source (From SDK 2.8.2) : Look for references to SYSPLL, there are plenty of them and I suspect that they should be removed or changed to AUDPLL

pll_error_t CLOCK_SetAudioPLLFreq(const pll_setup_t *pSetup)
{
if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)
{
/* Turn on the ext clock if system pll input select clk_in */
CLOCK_Enable_SysOsc(true);
}
/* Enable power VD3 for PLLs */
POWER_SetPLL();
/* Power off Audio PLL during setup changes */
POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);

/* Write Audio PLL setup data */
SYSCON->AUDPLLCTRL = pSetup->pllctrl;
SYSCON->AUDPLLFRAC = pSetup->audpllfrac;
SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1UL << SYSCON_AUDPLLFRAC_REQ_SHIFT); /* latch */
SYSCON->AUDPLLNDEC = pSetup->pllndec;
SYSCON->AUDPLLNDEC = pSetup->pllndec | (1UL << SYSCON_AUDPLLNDEC_NREQ_SHIFT); /* latch */
SYSCON->AUDPLLPDEC = pSetup->pllpdec;
SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1UL << SYSCON_AUDPLLPDEC_PREQ_SHIFT); /* latch */
SYSCON->AUDPLLMDEC = pSetup->pllmdec;
SYSCON->AUDPLLMDEC = pSetup->pllmdec | (1UL << SYSCON_AUDPLLMDEC_MREQ_SHIFT); /* latch */
SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(1); /* disable fractional function */

/* Flags for lock or power on */
if ((pSetup->flags & (PLL_SETUPFLAG_POWERUP | PLL_SETUPFLAG_WAITLOCK)) != 0U)
{
/* If turning the PLL back on, perform the following sequence to accelerate PLL lock */
uint32_t maxCCO = (1UL << 18U) | 0x5dd2U; /* CCO = 1.6Ghz + MDEC enabled*/
uint32_t curSSCTRL = SYSCON->SYSPLLMDEC & ~(1UL << 17U);

/* Initialize and power up PLL */
SYSCON->SYSPLLMDEC = maxCCO;   <<<< This is completely wrong! This will change the main clock PLL setting which races the PLL and makes the CPU crash
POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);

/* Set mreq to activate */
SYSCON->SYSPLLMDEC = maxCCO | (1UL << 17U);

/* Delay for 72 uSec @ 12Mhz */
SDK_DelayAtLeastUs(72U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);

/* clear mreq to prepare for restoring mreq */
SYSCON->SYSPLLMDEC = curSSCTRL;

/* set original value back and activate */
SYSCON->SYSPLLMDEC = curSSCTRL | (1UL << 17U);

/* Enable peripheral states by setting low */
POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
}
if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
{
while (CLOCK_IsAudioPLLLocked() == false)
{
}
}

/* Update current programmed PLL rate var */
s_Audio_Pll_Freq = pSetup->pllRate;

return kStatus_PLL_Success;
}

[Alice_Yang]

Hello,

It seems yes, while I haven't find a demo that use this function, you can first comment out 

them.