LPC54102 mail box interrupt on NVIC after wake up from Deep_Sleep or Power_Down

[knishi]

Hi,

I am investigating the LPC54102 chip and try to find out the mailbox function with the LPC Open examples and heart rate monitor example.

When I enable the NVIC MAILBOX_IRQn and create the interrupt handler for MAILBOX in the heartrate M0+ example, the MAILBOX_IRQn seems triggering whenever the device is waking up from the Deep_Sleep or Power_Down mode in addition to appropriate timing.

It is working as intended when the low power mode is set to the sleep mode.

Could somebody explain why Mailbox interrupt triggers with Deep_Sleep or Power_Down and does not trigger with sleep mode and suggests some methods to avoid triggering MAILBOX_IRQn, other than disabling the MAILBOX_IRQn?

Thank you for help in advance.

[isaacavila]

Hello Knishi,

Mailbox IRQ is triggered by internal code by writting non-zero values to IRQ0/IRQ1 registers, but not by external events, so in principle during deep sleep or power down, mailbox IRQ can't happen.

If Mailbox IRQ is entered on wake up, you can check

1. which core enters mailbox IRQ,

2. the IRQ0/IRQ1 values to confirm if the IRQ is triggered by software (Don't forget to clear IRQ0/IRQ1 to 0 in mailbox ISR). 

3. The value of CPU core's IPSR register to see if it is indeed the mailbox IRQ (Cortex-M4 has a known issue that makes the core fetching wrong vector in a rare case). 

Here is a quick workaround before locating the root cause: make sure IRQ0/IRQ1 are cleared in mailbox ISR, and if mailbox IRQ occurs, check the IRQ0/IRQ1 values, if the values can't be recognized then ignore the mailbox IRQ.

You can check multicore examples in LPCOpen for more details,

Hope this helps!

Regars

Isaac