LPC1857 C_CAN0 Interrupt problem

[lpcware]

Content originally posted in LPCWare by Yannick.C on Tue Feb 24 05:26:54 MST 2015
Dear All,

When an interruption is triggered on C_CAN0 the program go to Hardfault handler. If I disable interrupts of the C_CAN0, it seems to work correctly.
If I change controller to C_CAN1, interrupt occurs without any troubles.

In UM10430 rev2.6 I think there is an error on Table 72 (NVIC interrupt sources). All vector offset are wrong (and overlap with previous) from the interrupt ID 37 (GPIO pin interrupt 5). I think offset for C_CAN0 is 0x10C instead of 0xFC. But the default startup.s do not have this problem so it's just a datasheet error.
I think the real problem is that C_CAN0 handler address is read from address 0x0C instead of 0x10C, 0x0C is the offset of Hardfault.

I have a LPC1857JET256 with a -Y revision (normally engeineering sample of the Rev A).

I really need to use interrupt and C_CAN0, is someone has encountered the same problem ?

Best regards,

Yannick

[lpcware]

Content originally posted in LPCWare by xianghuiwang on Fri Apr 17 11:40:54 MST 2015
hi, Thanks for pointing out the issue in the UM. We will correct it.
For your development benefit, can you use the LPCOpen example periph_ccan example for a try?
http://www.lpcware.com/content/nxpfile/lpcopen-software-development-platform-lpc18xx-packages-0

regards,

[lpcware]

Content originally posted in LPCWare by SteveO on Wed Apr 15 17:21:39 MST 2015
I'm not using CAN0, so I can't answer your question.  I agree that all the vector offsets above PIN_INT4 in Table 73 appear to be wrong.  0x10c appears to be what was intended for C_CAN0.

Hardfault usually occurs when your ISR reads or writes an invalid address, like when a pointer is not initialized. However, that doesn't explain why CAN1 works.

ETA: Check Errata sheet item 3.1  "Writes to CAN registers write through to other peripherals"