LPC1800 Ethernet Tx underflow

[lpcware]

Content originally posted in LPCWare by Grant.Edwards on Thu May 16 14:19:57 MST 2013

I'm having problems with tx underflow errors on an LPC1857 eval board
from Keil.

Any time I attempt to send a packet longer than about 300 bytes, I
get a tx underflow error, and the tx side of the the Ethernet
controller locks up until it is reset.  I've tried DMA burst lengths
of 1,8,16, and 64: they all behave the same.  I don't seem to have any
problem receiving long packets.

I've also noted that when I send packets shorter than 300 bytes, I
have about 10-15% packet loss: all of the the packets appear to be
sent (link LED flashes), but 10-15% of them are invalid and get
dropped by the receiving device(s).  I've tried a variety of devices
on the "other end" and I get the same 10-15% packet loss with all of
them.

My M3 clock is 120MHz, and the Ethernet link is running at 100Mb
full duplex.  The Ethernet descriptors and buffers are all in SDRAM
that's also running at 120Mhz.

Any advice on how to get Ethernet tx to work?

[lpcware]

Content originally posted in LPCWare by Grant.Edwards on Fri May 17 08:13:22 MST 2013

The transmit underflow was apparently caused by the fact that I was running my program in SDRAM at the remapped address raange starting at 0x0000_0000 while the DMA controller was using SDRAM via the physical bus address range starting at 0x2800_0000. Relinking my program so that it ran at 0x2800_0000 eliminated the tx underflow lockup problem.

Is that restriction documented somewhere?

The tx packet loss was caused by my forgetting two things: disable the glitch filter on the 50MHz RMII clock input pin, and enable high slew rate for the RMII TX enable and TX data pins. Once the glitch filter was disabled and high slew rate drivers enabled, I didn't see any packet loss.