Hello all,
I am observing inconsistent behavior on the SPI bus implemented in the SSP peripheral on LPC1768.
Is there a restriction on keeping the SSP TX FIFO empty while data is being received by the RX FIFO and then start to send?
- Issue:
- Data written to the register is sporadically discarded/lost in SPI and not sent by LPC1768 (observed with a logic analyzer).
- The problem occurs in 15% of cases.
- Implementation Details:
- LPC1768 operating as SPI slave (SSP peripheral).
- Peripheral clock: 100MHz.
- Bus clock: 1500kHz (SSP0CPSR.CPSDVSR = 0x42, SSP0CR0.src=0x00).
- Read and write via IRQ Handler.
- Data is consumed using extremely stable circular buffer.
- No RX overrun events observed.
- Precondition:
- The master device is constantly sending data to the bus.
- LPC1768 firmware does not write to the DATA register (SSP0DR) when there is no data to send.
- Status register (SSP0SR) indicates "TX FIFO empty" (SSP0SR.TFE == 0x01).
- Scenario where the problem occurs:
- When there is data to be sent, the SSP TX interrupt is enabled (SSP0IMSC.TXIM = 0x01) and the handler writes the data sequentially to SSP0DR while there is space in the TX FIFO (SSP0SR.TNF == 0x01).
- How the problem manifests:
- Using a logic analyzer, it is observed that, in 15% of cases, the first byte is not sent by the bus to the master. It gets lost.
- When the problem occurs, these are the register values before and after writing the first byte to DATA:
- Before writing the first byte to SSP0DR:
- a) SSP0MIS: 0x00000008 or 0x0000000C
- b) SSP0SR: 0x00000003 or 0x00000013 or 0x00000017
- After writing the first byte to SSP0DR:
- a) SSP0SR: 0x00000016 or 0x00000017
- Before writing the first byte to SSP0DR:
Best Regards, Wagner Popov
