LPC1549 WWDT not running [SOLVED]

[lpcware]

Content originally posted in LPCWare by EtaPhi on Fri Feb 20 06:24:19 MST 2015
Hello!

I'm extending NXP IEC60335 library, because it doesn't check if WWDT is working and because some other security tests are missing (eg DMA controller test).

My code is simple.

After Cortex M3 registers test are passed, I look at SYSRSTSTAT register to find the reset source.

If WWDT forced a reset, a "magic number", which is stored in RAM, allows to tell a WWDT diagnostic reset from an unexpected one, so that the right action is taken.

If a Power-On, System or External reset restarted the core, WWDT dignostic code is executed.
This code sets bit 22 of SYSAHBCLKCTRL0 to feed the clock to WWDT bus interface.
Then bit 20 of PDRUNCFG is cleared to enable WDTOSC.
WWDT is then activated by storing 0x21 = WDEN + WDLOCK in WDMOD register.
About 100 clock cycles are then wasted to wait at least 3 WDCLK cycles (the core is running @ 12 MHz; WDTOSC frequency should be 504 kHz) so that changes to WDMOD register may take effect.
My code then sends the sequence 0xAA 0x55 to the FEED register to start WWDT.
It finally reads WWDT TV register to check if WWDT started, but its value is always 0xFF.
Since there is a delay of 6 WDCLK cycles between two reads, I suppose that WDTOSC isn't running.

Why is WDTOSC not running?

If this behavoiur happens only during debug, how can I test my code?

BR

EtaPhi

[lpcware]

Content originally posted in LPCWare by EtaPhi on Sun Mar 08 03:03:56 MST 2015
I solved my issues with watchdog.

I was wrong when I said that the watchdog is disabled during a debug session.

I succeded in debugging my watchdog code.
Of course, it's impossible to set a breakpoint which is going to suspend execution while the watchdog is active because the watchdog generates a reset which disconnects the debugging probe.

The root of my issues is the WWDT_WDMOD_WDPROTECT bit in WD_MOD register. When I set this bit, the watchdog fails to start.
It may be a my fault, but the LPCOpen example does not show its use.

By the way, I found an error in the following statement of rev. 1.1 UM10736 (page 299):

---

Quote:

The Watchdog interrupt flag is set when the Watchdog counter reaches the value
specified by WARNINT. This flag is cleared when any reset occurs, and is cleared by
software by writing a 0 to this bit.

---

The error lies in the clearing sequence which must write a 1 to reset WDINT flag.
The LPCOpen driver (wwdt_15xx.c) is correct, since it contains the following code:

/* Clear WWDT interrupt status flags */
void Chip_WWDT_ClearStatusFlag(LPC_WWDT_T *pWWDT, uint32_t status)
{
if (status & WWDT_WDMOD_WDTOF) {
pWWDT->MOD &= (~WWDT_WDMOD_WDTOF) & WWDT_WDMOD_BITMASK;
}

if (status & WWDT_WDMOD_WDINT) {
pWWDT->MOD |= WWDT_WDMOD_WDINT;
}
}

Regards,

EtaPhi

[lpcware]

Content originally posted in LPCWare by EtaPhi on Sat Feb 21 03:43:09 MST 2015
Of course I followed WWDT example, embd02161991!

The LPCOpen example can't be debugged too, because WWDT seems to be locked. Perhaps, LPCXpresso debugging tool chain disables WDOsc by using an undocumented feature.
As far as I can see, WWDT example runs fine on my LPCXpresso 1549 board  when it's standalone, but there is no way to debug it.

My code follows what LPCOpen WWDT example does, but it's written in assembly because it replaces NXP IEC60335 code (i.e. Power On Self Test function) which is written in assembly too and runs before that C runtime is initialized.

I'm a little concerned about LPC1549 safety, because if a debugger can disable WWDT by using an undocumented feature, there is a (little) probability that a misbehaving code may disable it too...

Thanks for your reply!

EtaPhi

[lpcware]

Content originally posted in LPCWare by embd02161991 on Fri Feb 20 14:43:57 MST 2015
Hi,

Have you used LPCOpen WWDT example ? May be its a good starting point.

http://www.lpcware.com/content/nxpfile/lpcopen-software-development-platform-lpc15xx-packages

Thanks,
NXP Technical Support