SystemCoreClock = 48000000
SysTick_Config(SystemCoreClock / 10000 / 30); <--- this one DOESN'T work
SysTick_Config(SystemCoreClock / 10); <--- this one works
When I set the SysTick_Config to the one on top, I cannot use EEPROM, but it works with the one at the bottom. Is there a range of restriction for SysTick_Config when using EEPROM?
Hi Lee Chen,
SysTick_Config(SystemCoreClock / 10000 / 30); will reduce the interval time between the SysTick interrupt versus SysTick_Config(SystemCoreClock / 10);
So you'd better to disable interrupt during EEPROM write and read operations.
Have a great day,
TIC
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Thank you for reply. Actually, I do have some USART and I2C devices with interrupt enabled. The way to enable interrupt for USART is thru USART1_4_IRQHandler and USART2_3_IRQHandler, and the way to enable I2C interrupt is thru static void i2c_iox_events(I2C_ID_T id, I2C_EVENT_T event).
Since those are functions that must be put in the code in order for USART and I2C to work normally. How is it possible to disable the interrupt if I must put these functions?
please refer below for those functions mentioned above:
void USART2_3_IRQHandler(void)
{
uint8_t res;
/* New data will be ignored if data not popped in time */
if ((Chip_UARTN_GetStatus(LPC_USART2) & UARTN_STAT_RXRDY) != 0)
{
res = Chip_UARTN_ReadByte(LPC_USART2);
Uart02Bf[USART2_RX_LEN++] = res;
if (USART2_RX_LEN == 26)
{
USART2_RX_LEN = 0;
FPreadFlag =0;
}
}
}
static void i2c_iox_events(I2C_ID_T id, I2C_EVENT_T event)
{
switch (event) {
case I2C_EVENT_DONE:
iox_xfer.rxBuff = &iox_data[1];
iox_xfer.rxSz = sizeof(iox_data);
iox_xfer.txBuff = (const uint8_t *) iox_data;
iox_xfer.txSz = sizeof(iox_data) + 1;
break;
case I2C_EVENT_SLAVE_RX://///////////////////////////////////////////////////////////////////////////////
iox_xfer.rxBuff = &iox_data[1];
iox_xfer.rxSz = sizeof(iox_data);
KeyInReadDataStatus = 1;
if(beepOn == 1)
{
if(beepSound == 1)
beep(); // beep!
}
LED_all_off();
uint32_t i;
for(i = 0 ; i < 180000 ; i++);
LED_all_on();
break;
case I2C_EVENT_SLAVE_TX:
if (iox_xfer.txSz == 1) {
iox_xfer.txBuff = (const uint8_t *) iox_data[0];
iox_xfer.txSz = sizeof(iox_data) + 1;
}
break;
}
}
Hi Lee Chen,
Thanks for your reply.
Please referring to the below code, and give a try.
/*****************************************************************************
** Function name: u32EEPROM_WRITE
**
** Description: Program the EEPROM with data stored in RAM.
**
** Parameters: u32DstAddr - Destination EEPROM address
** u32SrcAddr - Source RAM address, should be a word boundary
** u32Len - Number of 8-bit bytes to write,
*
** Returned value: Status code returned by EEPROM ROM function.
**
******************************************************************************/
uint32_t u32EEPROM_WRITE(uint32_t u32DstAddr, uint32_t u32SrcAddr, uint32_t u32Len)
{
uint32_t au32Result[3];
uint32_t au32Command[5];
au32Command[0] = EEPROM_CMD_WRITE;
au32Command[1] = u32DstAddr;
au32Command[2] = u32SrcAddr;
au32Command[3] = u32Len;
au32Command[4] = SystemCoreClock / 1000UL; /* Core clock frequency in kHz */
__disable_irq();
EEPROM_EXECUTE_CMD(au32Command, au32Result);
__enable_irq();
return au32Result[0];
}
/*****************************************************************************
** Function name: u32EEPROM_READ
**
** Description: Program the EEPROM with data stored in RAM.
**
** Parameters: u32DstAddr - Source EEPROM address
** u32SrcAddr - Destination RAM address, should be a word boundary
** u32Len - Number of 8-bit bytes to write,
*
** Returned value: Status code returned by EEPROM ROM function.
**
******************************************************************************/
uint32_t u32EEPROM_READ(uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32Len)
{
uint32_t au32Result[3];
uint32_t au32Command[5];
au32Command[0] = EEPROM_CMD_READ;
au32Command[1] = u32SrcAddr;
au32Command[2] = u32DstAddr;
au32Command[3] = u32Len;
au32Command[4] = SystemCoreClock / 1000UL; /* Core clock frequency in kHz */
__disable_irq();
EEPROM_EXECUTE_CMD(au32Command, au32Result);
__enable_irq();
return au32Result[0];
}
Have a great day,
TIC
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Hi Jeremy,
I think it works!
so all I need to do is making sure wrapping my IAP command with __disable_irq(); and __enable_irq(); right?
like this:
…….
__disable_irq();
iap_entry(command, result);
__enable_irq();
…...
Hi Lee Chen,
Thanks for your reply.
When the IAP routines are used, any access to the flash memory must be avoided during the erase and write operations. If the vector table interrupt is located in the flash, all the interrupts must be disabled prior to erase and write.
You can learn the guide of IAP calling in the attachment and please checking it for details.
Have a great day,
TIC
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Do you mean there cannot be any interrupt during EEPROM read/write? or do you mean I need to disable the interrupt function even if I don't receive any interrupt during EEPROM read/write?
Hi Lee Chen,
Thanks for your reply.
1) Do you mean there cannot be any interrupt during EEPROM read/write? or do you mean I need to disable the interrupt function even if I don't receive any interrupt during EEPROM read/write?
-- Yes.
Have a great day,
TIC
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