Hi Paolo Bernasconi，
1) Does LPC11U6x has a flash accelerator ?
No, it doesn't have it.
2) If I run the CPU at 50Mhz what is the average CPI fo fetch an instruction form the flash ?
The cycle counts is depend the particular instruction and wait-states configuration.
I've attached the Cortex 0+Technical Reference Manual and you can find the Cortex-M0+ instructions and their cycle counts in the Table 3-1.
3)In the user manual I see the register that set a number of wait cycle depending on the CPU frequency (3 cycles if CPU ? 50Mhz) In case no flash accelerator is available is this the number of wait cycle I have to wait ?
Yes.
4) How is possible to move an ISR function from flash to RAM using LPCxpresso copy it automatically by the c startup code ?
I've attached the application note: AN11511, it has illustrated the approach of relocating the interrupt table to the SRAM in the section 5.1.4.
Have a great day,
Ping
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