IAP sector erase problem in LPC17xx

[lpcware]

Content originally posted in LPCWare by mostafanfs on Wed Apr 06 03:03:57 MST 2016
I've been working with IAP flash programming and I encountered a problem I couldn't figure out.
I'm using IAR on a LPC1778 board and I have written a function and I've placed it in the last sector which is sector #29 (out of sector #0 to sector #29) so it would be able to read new firmware from an external flash and write it to sectors #1 to #28 after erasing them. (sector #0 is not affected in the whole process)

Problem is when I erase sector #1 before copying RAM to Flash the program execution gets messed up and it just blows (I'm in IAR debugger with connected jlink performing step by step debugging) and therefore it does not return a Return Code and I'm not able to figure out the problem.

But if I determine sector #2 as the first sector to be erased it works just well and I can copy entire new firmware into flash starting from sector #2 .
But I want to begin with sector #1 .
Obviously it has something to do with the sector #1 when it comes to erasing sectors before copying to flash.

This is my icf (linker) file. I have edited some addresses :

/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00001000;
define symbol __ICFEDIT_version_start__ = 0x00002000;
/*-Memory Regions-*/
define symbol __BOOTLOADER_START__ = 0x00078000;
define symbol __BOOTLOADER_END__ = 0x0007FFFF;
define symbol __ICFEDIT_region_UPDATE_IMAGE_ROM_start__ = 0x00001000;
define symbol __ICFEDIT_region_UPDATE_IMAGE_ROM_end__   = 0x00067FFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x10000000;
define symbol __ICFEDIT_region_RAM_end__   = 0x1000FFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__   = 0x5000;
/**** End of ICF editor section. ###ICF###*/

define symbol __RAM1_start__  = 0x20000000;
define symbol __RAM1_end__    = 0x20002FFF;
define symbol __RAM2_start__  = 0x20003000;
define symbol __RAM2_end__    = 0x20007FFF;

define memory mem with size = 4G;
define region BOOTLOADER_region   = mem:[from __BOOTLOADER_START__ to __BOOTLOADER_END__];
define region UPDATE_IMAGE_ROM_region   = mem:[from __ICFEDIT_region_UPDATE_IMAGE_ROM_start__ to __ICFEDIT_region_UPDATE_IMAGE_ROM_end__];
define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
define region RAM1_region  = mem:[from __RAM1_start__ to __RAM1_end__];
define region RAM2_region  = mem:[from __RAM2_start__ to __RAM2_end__];

define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };

initialize by copy { readwrite };
do not initialize  { section .noinit };

place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place at address mem:__ICFEDIT_version_start__  { section .rodata object version.o };
place in UPDATE_IMAGE_ROM_region   { readonly }; 
place in BOOTLOADER_region   { section BOOTLOADER_SECTOR };
place in RAM_region   { readwrite, block CSTACK };
place in RAM1_region  { section .sram, section PERRAM };
place in RAM2_region  { block HEAP };

Where does interrupt vectors are located?
Could it be the reason ? (of course I've disabled all interrupts before playing around with IAP)

[lpcware]

bump

[lpcware]

Content originally posted in LPCWare by mostafanfs on Thu Apr 07 00:30:46 MST 2016

---

Quote: robert hulsebos
Interrupt vectors are at address 0 after startup and remain there unless you relocate them (VTOR register).
Anyway, best approach is to make sure interrupts are disabled during your IAP calls, because if I remember correctly the ROM API makes some temporary changes to the memory map while it is active. Our experience is that an interrupt while processor is busy in IAP may cause the processor to crash. At least it is with LPC1769. I am not sure if the same applies for LPC1778...

---

Yeah I mentioned I have disabled all interrupts using __disable_irq() and I don't need any interrupts for that matter.
The thing is with the sector #1 that whenever I try to erase it it just blows.
I checked and VTOR register has been assigned with 0x00001000 (so I guess it's sector #1) . Could that be the reason?
If that is the case then where would I put it?
It has been done in system_LPC177x_8x.c file which has came from NXP samples I guess. So I figured it was ok.

Also another question. What data are located in sector #0 ?
I took this board from a company and apparently there is a .bin file which is supposed to be programmed at 0x00000000 address or it wouldn't work. Unfortunately it's a .bin file and I can't make much sense out of it obviously. I just know I;m supposed to program it there at address 0x00000000 with jFlash utility. As you see I got the linker file (.icf in first post) from this company and they have remarked 0x00001000 address (sector #1) as you see in following symbol :
define symbol __ICFEDIT_region_UPDATE_IMAGE_ROM_start__ = 0x00001000;

But then there is another symbol marking the location of interrupt vectors (.intvec section)
define symbol __ICFEDIT_intvec_start__ = 0x00001000;
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };

So it's the same as ROM_Start address and both are sector #1 (0x00001000)

So what is this .bin file located in 0x00000000 address (sector #0) doing here ? is it some sort of jumping to sector #1 in there?
Why couldn't I put my application in sector #1 without programming anything in sector #0 ?
I mean what is the execution sequence in the processor? If there is nothing in sector #0 shouldn't it be able to jump to sector #1 where there is a valid program waiting for execution ?


Could I just simply assign 0x00000000 to VTOR and put .intvec section and ROM_start at 0x00000000 (in linker file) and not program that crazy .bin file in sector #0 anymore? I think it should work even though I don't have access to my board right now.


Sorry for asking too much. I'm just confused.

[lpcware]

Content originally posted in LPCWare by robert hulsebos on Wed Apr 06 03:46:26 MST 2016
Interrupt vectors are at address 0 after startup and remain there unless you relocate them (VTOR register).
Anyway, best approach is to make sure interrupts are disabled during your IAP calls, because if I remember correctly the ROM API makes some temporary changes to the memory map while it is active. Our experience is that an interrupt while processor is busy in IAP may cause the processor to crash. At least it is with LPC1769. I am not sure if the same applies for LPC1778...