Hw trigger ADC using CT timers

[kulkar68]

Hello, 
I am using the LPC55s69 Dev kit
I need to configure the ADC to be triggered from an CT timers. and then the DMA to copy the data to RAM.
I am using the SDK 2.6.3. 
 whats needed:use an CT as a HW trigger and have the dma automatically copying data into a Ram buffer. 
Any help would be appreciated

Regards,
Sushant Kulkarni

[kulkar68]

Need to convert sw triggered sdk example to hw trigger . please provide configuration and other chnages required .

[Alice_Yang]

Hello Sushant,

There are Ctimer, ADC and DMA demos under SDK, you can refer to.

BTW, recommend you use the latest version of SDKv2.7.1.

Have a great day,
TIC

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[kulkar68]

continue from above mail:

Also do i need to enable Interrupt or callback function

[Alice_Yang]

Hello sushant ,

- Please first try to use software trigger ADC, whether it can work well?

- If software trigger can work, set the EMC3 of Timer external match registers(EMR) to 0x2.

[danielholala]

Dear @Alice_Yang ,

you suggest to set EMC3 (in the external match register EMR of the timer) to 0x2. This bit means "Set the corresponding External Match bit/output EM3 to 1". Thus when a match occurs between the TC and MR3, the EM3 bit is set and generates the corresponding ADC trigger (if enabled).

However, the manual also states "hardware trigger events are detected on the rising-edge of the associated hardware trigger source.". Thus until the EM3 bit in EMC is reset, no further hardware trigger through CTIMER will occur. 

How do you suggest to handle this problem? Reset EM3 bit through ADC ISR?

Instead, I've set EMC3 to 0x3, that is "Toggle EM3 bit". This triggers ADC on every other timer cycle: The first timer match sets the EM3 bit which in turn generates the ADC hardware trigger. The next timer match resets the EM3 bit. This effectively reduces the trigger frequency by 2.

[kulkar68]

Hello Alice,

I am modifying existing lpadc_dma example provided with SDK

i checked all peripheral ADC, Ctimer and DMA individually. problem is with integration of all three.

I have configured following:

ADC:

enabled hardware trigger 5

5 State Counter Timer (CTIMER) ct0_mat3_out via TCTRLa[HTEN] for index 5

TCTRLa[TPRI] is kept 0 

Ctimer:

#define CTIMER CTIMER0 /* Timer 0 */
#define CTIMER_MAT_OUT kCTIMER_Match_3 /* Match output 3 */
#define CTIMER_CLK_FREQ CLOCK_GetCTimerClkFreq(2U)

config:

matchConfig.enableCounterReset = true;
matchConfig.enableCounterStop = false;
matchConfig.matchValue = CTIMER_CLK_FREQ / 4;
matchConfig.outControl = kCTIMER_Output_Toggle;
matchConfig.outPinInitState = true;
matchConfig.enableInterrupt = false;
CTIMER_SetupMatch(CTIMER, CTIMER_MAT_OUT, &matchConfig);

DMA  :

No modification from Lpadc_dma example.

Changes in main:

Removed getchar() and LPADC_DoSoftwareTrigger(). and called CTIMER_StartTimer(CTIMER) before while(1)

my understanding:

i/p: continious square wave from function generator on P28 on board 

As the ctimer value reaches the matchvalue , CTIMER_MAT_OUT (which is mat_out_3) performs togle operation and reloads timer . 

mat_out_3 rising edge acts as hardware trigger to ADC and after conversion it should trigger DMA to transfer from FIFO to ram .

but not able to see output in FIFO or ram variable . so ADC is not triggered .

Please do tell if any configuration is missing or function call to be done in main.