Can I use SDR CLK1 instead of SDR CLK0 for 128Mb x16 single-chip SDRAM?

[lpcware]

Content originally posted in LPCWare by darkknight on Mon Jul 16 08:54:28 MST 2012
Hello All,

I have a question regarding the LPC1830 SDRAM interface. As you know very well, there are four possible SDRAM clock pins (CLK0 - CLK3). I have a single-chip 128Mb x16 SDRAM in my design. Initially, I was thinking about bringing EMC_CLK0 (SDRAM clock 0) from the processor to the SDRAM. However, I noticed that, if I assign CLK1 (SDRAM clock 1) as my SDRAM clock, the layout will be easier and I will not have to use any vias on that clock signal. That's because CLK1 pin is T10, which is an edge pin on the BGA. Also, if I can use CLK1 as the SDRAM clock, do I have to then use CKE1 instead of CKE0 for clock enable pin? Basically, if I use the following signals for the SDRAM interface, will there be any issue?

CLK1 - SDRAM clock
EMC_CKEOUT0 - SDRAM clock enable 0
EMC_DYCS0 - SDRAM chip select 0

Thank you for your help.

[lpcware]

Content originally posted in LPCWare by darkknight on Mon Jul 16 20:22:43 MST 2012
Hello Kevin,

Thanks for detailing the sdr interface to me. I can use the dycs1/cke1/clk1 group as you had recommended. I have another question regarding that. Will EMC controller know which group I am using based on whether I am specifying dycs0 or dycs1 group in the initialization header (i.e. pin-mux). For example, dycs0 pin is muxed with gpio3[5] and t2-mat2. So, if I don't select dycs0 function for p6_9 and select dycs1 function on its specified pin, will the sdr controller know it that way which group is being used? Or, it's just matter of setting different address range?

You had mentioned that the dram initialization will be different for the dycs1 group. What has to be dffferent between init for dycs0 and dycs1?

Thanks for all of your help.

--
Fazlul Karim
Comtrol corp.

[lpcware]

Content originally posted in LPCWare by wellsk on Mon Jul 16 12:35:04 MST 2012
To keep DRAM power usage down, the DRAM controller may disable signals for DRAM chip selects that are inactive. (See the DYNAMICCONTROL register in the EMC block).

<code>
CLK1 - SDRAM clock
EMC_CKEOUT0 - SDRAM clock enable 0
EMC_DYCS0 - SDRAM chip select 0
</code>
In the case above with DRAM CLK1, CKE0, and DYCS0 - CLK0 will be active while CLK1 is inactive when DYCS0 and CKE0 are enabled on the DRAM access of DYCS0. This is with the DYNAMICCONTROL CS bit set to 0 which is the recommended state. You could force the DRAM CLK1 signal to remain active (not gated with CKE1) by setting the CS, but your power usage will suffer. In you need the lower power self-refresh DRAM state, you won't be able to place the DRAM into this state without the hardware gating between the matching CKEx and CLKx signals.

So don't mix these signals. If you don't want to use DYCS0/CKE0/CLK0 as a group, you can use DYCS1/CKE1/CLK1 group instead (and only have to deal with a different DRAM address range and some edits on DRAM init).