4 x SDRAM at LPC43x7

[lpcware]

Content originally posted in LPCWare by khfreiberg on Mon Dec 02 16:23:12 MST 2013
Hi,
I have 4 x MT48LC64M8A2 (-75) at dynCS1 to use the full 256MB. It is a brand new prototype board.
EMC is running at 204/2MHz. I have problems with the setup. My little RAM test works fine at first run. But when I read the data again they change. The changed data seems to be stable with a '00' in chip 1 and 'FF' in chip 2. Other data are shifted by 4 byte in address. Looks like a refresh issue. I would like to distinguish between layout problem and setup failure. But when I search examples and forum entries it seems like everybody has it's own magic. Especially strange is the multiple calling of 'LPC_EMC->DYNAMICREFRESH' where the shown values doesn't match 'UM10503'. Additionally I am not sure how to calculate the offset for WR_MODE (12?, 14?) for 4 chips. Both values don't change behavior. Does anybody have a working setup that I can use as platform for further investigations?
I would appreciate any help.

Greetings

[lpcware]

Content originally posted in LPCWare by khfreiberg on Tue Dec 03 10:53:15 MST 2013
Thanks,
I have this Excel sheet. I tested at lower clock speed and the behavior changed. I still have this jump in address. I am filling the RAM with up-counting values, and read it back immediately after filling. That works fine. But when I read it back later on using an USB interface or even a RAM window in uVision I see this jump of 4 bit back in address. Thanks for the mode set up. What's still confusing me is 'LPC_EMC->DYNAMICREFRESH'. When I read the manual I should use '7.8us * 204MHz/2 / 16(+1) cycl'. But in examples I see two programmings where the second call deals with '15625'. I have no clue where this number is coming from. Additionally, I do not see how examples matches the initialization procedure in the RAM data sheet. It talks about two 'AUTO REFRESH' cycles. I assume this is the 'PALL' command. I see only one. But I see multiple NOP commands. What are they doing? This is the magic I mean ;-))   

Greetings,

[lpcware]

Content originally posted in LPCWare by bavarian on Tue Dec 03 09:42:02 MST 2013
Hi,

my first recommendation is that you test your setup at a lower SDRAM speed. Maybe you've done everything correct but you run into the problem EMC.1 described in the error sheet.
If it works at lower speed the workaround could be to add a small capacitor (5 ... 15pF) to the SDRAM_CLK to delay the clock signal a little bit.

The correct initialization of the SDRAM is of course important, but not really magic.

I attached an Excel file which might help with the register programming.
It is for the MT48LC4M32B2, you need to adapt it to the MT48LC64M8A2

The mode register:

// Write the SDRAM mode register
// Mode register bits: see also data sheet of the SDRAM
// M0-M2 specify the burst length: 011 = burst length of 8 (always!!)
// M3 specifies the type of burst (sequential or interleaved): 0 = sequential (always!!)
// M4- M6 specify the CAS latency: 2 
// M7 and M8 specify the operating mode: 00 = standard operation (always!!)
// M9 specifies the WRITE burst mode: 0 = programmed burst length  (always!!)
// M10 and M11 are reserved for future use
//
// This mode register value needs to be shifted by a specific number of bits:
// Column address bits: 10  (A0 - A9)
// 4 banks:                   2
// RBC mapping:         1
//                     ---
//                      13

Hope this brings you forward,
NXP Support Team