e8011 eDMA errata workaround

[mjbcswitzerland]

Hi

In a K02F based product there have been complication due to the e8011 eDMA errata and the workaround has not yet proved to be successful.

DMA Channel 0 is used for memory to memory transfers
DMA Channel 1 or UART0 Tx operation
DMA Channel 2 or UART1 Tx operation

With high activity the channel 0 failed occasionally with three main failure types:
1. The destination pointer would be corrupted (for example it would take one of the UART's pointers) and a channel error flag is set
2. A configuration error is signaled although the configuration problem is not visible
3. No error is signaled but the DONE bit is never set

After applying the workaround where the SADDR, DADDR, and NBYTES are checked and re-written if not read back identically the first two failure types are eliminated but the third type still occurs.
If DMA operation is not used on the UARTs there are no further issues (and the memory to memory transfers are reliable).

This gives the following two questions:

1. Why doesn't the particular workaround solve the third error type?
2. Is there reference code as to the typical workaround for verification?

The second potential workaround hasn't been tried yet since it is not fully clear:

1) Halt the DMA via the HALT bit or by disabling each channel.

2) Verify DMA is inactive via the ACTIVE bit.

3) Write the TCD information.

4) Re-enable the DMA (clear the HALT bit or enable each channel).

Questions:
- to 2) There is an active bit for each channel - does each channel need to be checked for activity and what needs to be done if it is active? Wait until it no longer signals activity?
- to 4) Should the new DMA transfer be enabled before or after this step?

Thanks in advance

Regards

Mark

[mjbcswitzerland]

Hi

The product development is using both K02F and K12 parts as alternative devices for supply chain purposes and the same code runs on both.
However the K02F based parts suffer from reliability problems due to the errata, and the errata workaround hasn't proved successful yet.

Can NXP help out since this is not normal code development but needs some insider knowledge to solve.

Thanks

Regards

Mark

[Robin_Shen]

Design team thinks that the only solution is this section:

Ensure that the eDMA is idle before writing TCD values by following this procedure:

1) Halt the DMA via the HALT bit or by disabling each channel.

2) Verify DMA is inactive via the ACTIVE bit.

3) Write the TCD information.

4) Re-enable the DMA (clear the HALT bit or enable each channel).

More specifically:

1. Halt the DMA via the control register
2. Read each TCD word7 bit 6 ACTIVE should be 0 (if not 0 wait for ALL channels to show not active)
3. Write each channel’s TCD
4. Write each channel’s start bit in TCD – word 7 bit0 = 1
5. Clear the halt bit in the control register

The second solution in the errata is not robust.  This has been fixed in future versions of the DMA.

[mjbcswitzerland]

Thank you Robin

We will try the alternative workaround.

Regards

Mark

[Robin_Shen]

Hi Mark,

Sorry for my late reply!
I will consult our internal team.

Best Regards,

Robin