What counts as a KE flash write/erase cycle?

[howardg]

The datasheet specifies 100K nominal write/erase cycle endurance for the KE part (FTMRE) we're using. But what constitutes a write/erase cycle?  The plain language is ambiguous.

In my application I write 4 bytes at a time to flash erasable in 512 byte sectors.  Restating my question to resolve the ambiguity for my application, will I expend 129 endurance cycles by filling up and erasing the sector (128 word writes+1 erase), or just 1 cycle?

Thanks in advance

[mjbcswitzerland]

Howard

The limit is effectively the number of times you erase the sector, which is restricted to 100k (guaranteed).

If you write one long word at a time (addressed sequentially) you can do this 64 times before a 512 byte sector is full. If you then want to write another long word to that sector you will need to erase it and start again This is one cycle and so you can write 6.4 million long words (with erases when necessary) before the sector has reached its life limit.

If you do the same in 4k of sectors it increases the overall number of long word writes possible to 51.2 million, etc.

Regards

Mark

[howardg]

Thank you very much, Mark. FWIW your understanding comports with my understanding of the technology but this golden oldie thread https://community.nxp.com/thread/424106 coupled with the datasheet wording gave me pause as they suggest a possible different mechanism that counts discrete writes against the endurance limit, despite it being less than reasonable and arguably a strained reading of the datasheet footnote.

I don't wish for you to do my work for me and appreciate your kindness.  My job this point requires confirmation from NXP to share with my product manager.  Hello NXP can you please check in? TIA

[mjbcswitzerland]

Howard

The other thread is about a different Flash technology from NXP before they took over Freescale and the Kinetis parts. Therefore I don't think that it has any relevancy to your case. I know the LPC flash quite well and it has a 128 bit write line, plus ECC in Flash that is saved with it. It doesn't allow modifying anything in a line after written since it causes the ECC of the complete line to become corrupted.

The trend to smaller silicon structures to save cost, reduce power and increase speed can have an adverse effect on the endurance and this is often offset be internal error correction techniques, but these tend to be secrets. There was no official details about the LPC flash internal operation originally but some were made available by a Philips application engineer which are summarised here:

http://www.utasker.com/forum/index.php?topic=136.msg488#msg488

I think that the KE's Flash is straightforward but I suspect some special behavior in the newer parts (like K64) since one can corrupt a 'line' of flash if one tries to write a phrase twice, which results in an area of flash that can't be read (it will hard fault if tried) until either a sector erase has been made (or even a mass erase?) recovers it.

If you need guaranteed endurance statement about a particular use you will of course need to get this from NXP directly.

Regards

Mark