S32K DMA TRANSFER MULTIPLE ADC CHANNELS

[yumi]

#S32K ADC DMA ：
Can DMA support more than 4 channels for transfering ADC result data on S32K142 ?
Now I want to sample 3 channels data from ADC0 instance,and they are triggered by FTM1->PDB0,
The DMA interrupt logic will get the rough data when ADC0 sampling got completed.
After referring to K14X-RM.pdf,I was told only [power-of-2 size bytes] can be supported for data queues,did it mean that I have to set SMOD to 4 even if 3 channels needed actually?
How I can set the relative registers for it ?
The source code are list below,right now DMA interrupt does not work,please help to correct it,so much appreciated in advance.

 DMA->TCD[0].CSR &= ~DMA_TCD_CSR_DONE_MASK;  
 DMA->TCD[0].ATTR = DMA_TCD_ATTR_SMOD(4)  |    /*does not work even if set to 0 */   
                                      DMA_TCD_ATTR_SSIZE(2) |      /*Source data transfer size32bit*/           
                                      DMA_TCD_ATTR_DMOD(0)  |             
                                      DMA_TCD_ATTR_DSIZE(2);        /*Destination data transfer size 32 bit*/     
 DMA->TCD[0].NBYTES.MLNO = DMA_TCD_NBYTES_MLNO_NBYTES(3);  
 DMA->TCD[0].CITER.ELINKNO = DMA_TCD_CITER_ELINKNO_CITER(3) | 
                                                        DMA_TCD_CITER_ELINKNO_ELINK(0);  
 DMA->TCD[0].BITER.ELINKNO = DMA_TCD_BITER_ELINKNO_BITER(3) | 
                                                        DMA_TCD_BITER_ELINKNO_ELINK(0);  
 DMA->TCD[0].SADDR = DMA_TCD_SADDR_SADDR(&(ADC0->R[2]));   
 DMA->TCD[0].SOFF  = DMA_TCD_SOFF_SOFF(4);     
 DMA->TCD[0].SLAST = DMA_TCD_SLAST_SLAST(0);       /*Last source address adjustment
Failed also when set it to -12=4byte/channel*3channel */
 DMA->TCD[0].DADDR = DMA_TCD_DADDR_DADDR(RecordBuf_ADC0); 
 DMA->TCD[0].DOFF  = DMA_TCD_DOFF_DOFF(4);
 DMA->TCD[0].DLASTSGA = DMA_TCD_DLASTSGA_DLASTSGA(-12);    
 DMA->TCD[0].CSR = DMA_TCD_CSR_BWC(0)         |          
                                    DMA_TCD_CSR_MAJORELINK(0)  |          
                                    DMA_TCD_CSR_MAJORLINKCH(0) |         
                                    DMA_TCD_CSR_ESG(0)         |                                  
                                    DMA_TCD_CSR_DREQ(0)        |         
                                    DMA_TCD_CSR_INTHALF(0)     |         
                                    DMA_TCD_CSR_INTMAJOR(1)    |         
                                    DMA_TCD_CSR_START(0);            

[PetrS]

Hi,

NBYTES must be set to 4, you are moving 32bit word (4 bytes) per single HW request.

Keep SMOD=0 and SLAST=-12.

This setting assumes 3 adjacent ADC result registers will be read, so ADC0->R[2],ADC0->R[3] and ADC0->R[4]

BR, Petr