Occassionaly seeing only LVD reset flag set but no POR flag set in k24 micro

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Occassionaly seeing only LVD reset flag set but no POR flag set in k24 micro

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ashok_gaddam
Contributor I

Hi,

I am occasionally seeing only LVD bit set but no POR bit set in reset source information when power is applied to my project hardware having k24 micro (MK24FN1M0VLL12R). I would expect both flags to be set when power is applied or any power cycle happens. Any thoughts on why sometimes the POR flag is not set when power is reapplied?

If there is any partial voltage holding by the hardware circuit (not fully discharged), can we see only the LVD flag during the fast power cycle attempts?

Regards,

Ashok

 

 

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diego_charles
NXP TechSupport
NXP TechSupport

Hi @ashok_gaddam 

I hope you are doing well!

After checking with a colleague,  he let me the following:

At power up (POR), the internal bandgap is not trimmed and the "default" LVD threshold may be lower than the trimmed LVD threshold. On power up, especially one with a slow ramping supply, after the default LVD threshold is reached and the system comes out of reset, both the POR and LVD bits in the SRS register will be set. If the trimmed LVD threshold is much higher than the default threshold once the trimmed threshold is set, the VDD may now be below this new trimmed value. This will result in a second reset occurring, which will be due to LVD. So once the code actually runs and the SRS register is read, it will only read the reset as LVD.

 

If you put a scope probe on the reset pin you should see it ramp up with VDD and then go low at ~1.2V (VPOR voltage) when POR is released. It will stay low until LVD is released (at ~1.55V to 1.65V) and should go high and stay high. However, if after going high after LVD releases, it drives low again then that would indicate the trimmed LVD threshold is what is causing this second reset and clearing the POR bit in the SRS. You may not see it drive low due to the external pull up and capacitance on the reset pin. You may need to remove these components to see this occur.

The suggestion of an external power supply will may "resolve" the issue and let you see both the POR and LVD bits being set in the SRS register if the power supply ramp rate is much faster than that on the board.

A very slow ramp, or noise, on the power supply voltage can also cause the POR bit to not appear set on a POR event.

 

 About a power cycling testing:

In the scenario of having the VDD connected and unconnected way to fast.  There exists the possibility that the VDD can only fall to  LVD threshold  before the VDD rises again. 

For example, VDD is disconnected for less than ~10 us  depending on the decoupling capacitance, it will not drop too far below LVD. In fact, if VDD equals to 3.3V it will require more than 10 us before it drops below POR threshold.
 
I hope this could help you. 
My apologies for the delay
 
Diego

 

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