Interaction between ports E and F on TWR-K70F120M

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Interaction between ports E and F on TWR-K70F120M

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DanielWillenson
Contributor I

I was trying to use some of the port F pins on the K70 to access some extra UARTs, when I noticed this strange behavior. Everything works fine as long as I enable port E in addition to port F, but if I leave port E disabled then none of the port F pins work as outputs. I confirmed that this is true, even if I'm just trying to use them as GPIO pins. Here's a sample program:

/*

* This program outputs a square wave on PTF14

* of the TWR-K70F120M board, which can be accessed

* as pin C56 of the TWR-ELEV secondary board

* expansion connector.

*

* Unfortunately, there is no output unless port E is

* enabled in addition to port F. Why???

*/

#include "derivative.h"

/* Change this to undef to prevent enabling of Port E. */

#define ENABLE_PORTE

int main(void)

{

  uint32_t count;

#ifdef ENABLE_PORTE

  SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK;

#endif

  SIM_SCGC5 |= SIM_SCGC5_PORTF_MASK;

  PORTF_PCR14 = PORT_PCR_MUX(0x1);

  GPIOF_PDDR |= 1 << 14;

  for (count = 0; ; count++) {

    GPIOF_PDOR = (count & 0x100000) >> 6;

  }

  return 0;

}

Does anyone have any insight into why port E has to be enabled in order to use port F as an output?

Thanks!

Daniel

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Mario_Guardado
Senior Contributor I

Hello Daniel,

This is a known issue on mask 1N96B, you can find the mask set errata document in the following link:

http://cache.freescale.com/files/microcontrollers/doc/errata/KINETIS_1N96B.pdf?fpsp=1&WT_TYPE=Errata...

*************************************************************************

e5234: GPIO: PORTF registers are not accessible unless SIM_SCGC5[PORTE] is set

Errata type: Errata

Description: The SIM_SCGC5[PORTF] bit does not enable the clock to the PORTF GPIO module. Instead,

the clock gate enable bit for PORTE enables the clock for both PORTE and PORTF.

Workaround: Set the SIM_SCGC5[PORTE] bit in order to access the PORTF registers.

*************************************************************************

It was solved on mask 3N96B.

Regards.

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Mario_Guardado
Senior Contributor I

Hello Daniel,

This is a known issue on mask 1N96B, you can find the mask set errata document in the following link:

http://cache.freescale.com/files/microcontrollers/doc/errata/KINETIS_1N96B.pdf?fpsp=1&WT_TYPE=Errata...

*************************************************************************

e5234: GPIO: PORTF registers are not accessible unless SIM_SCGC5[PORTE] is set

Errata type: Errata

Description: The SIM_SCGC5[PORTF] bit does not enable the clock to the PORTF GPIO module. Instead,

the clock gate enable bit for PORTE enables the clock for both PORTE and PORTF.

Workaround: Set the SIM_SCGC5[PORTE] bit in order to access the PORTF registers.

*************************************************************************

It was solved on mask 3N96B.

Regards.

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