GPIO HI-Impedance configuration and pullup/pulldown in MK20DX series ?

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GPIO HI-Impedance configuration and pullup/pulldown in MK20DX series ?

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michelecanepa
Contributor I

Dear Sirs,

I have few questions:

  1. Does anyone knows if there's the possibility to configure the GPIO pins on K20 Sub-family microcontrollers MK20DX64VLH7, MK20DX128VLH7, MK20DX256VLH7 to put them in HI-Z status?
  2. The GPIO's do have a pullup or a pulldown? In what GPIO conditions?
  3. Are there different strengths for the GPIOs current capability? Are the strengths configurable, or there are differences from pin to pin?
  4. In reset condition, or start-up condition, what is the GPIO status, in term of direction, pullup configuration, output status?

I could not find that information on the documents I've read, that are:

K20P64M72SF1

Rev. 3, 11/2012

K20P64M72SF1RM

Rev. 1.1, Dec 2012

Do I need any other document?

Thank you everybody.

Best regards,

Michele Canepa, Electrical Engineer.

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egoodii
Senior Contributor III

Referencing:

K20P64M72SF1RM

Rev. 1.1, Dec 2012

1 - All GPIO are 'Hi-Z' when configured as inputs -- see 49.2.6.

2 - Most GPIO pins have the options under 'PORT control' 11.14.1, the pull-enable and up/down being the two LSBs.

3 - See above -- also a function of PORT control.

4 - All GPIO pins will be 'input' (Hi-Z) as per the 'reset condition' outlined in 49.2.6.  However, for a complete definition of 'pin state at reset' refer to chapter 10.  10.2.2 lists some 'special' reset-values for some members of Port A PORT control, but more particularly the table in 10.3.1 lists the 'default' operational-mode for every pin on the package.  Most pins default to their 'analog' function -- Alternate '0' --  (except the debug pins, on Port A, as selected by those 'special' PORT control values), as this has the least restriction on external connections.

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egoodii
Senior Contributor III

Referencing:

K20P64M72SF1RM

Rev. 1.1, Dec 2012

1 - All GPIO are 'Hi-Z' when configured as inputs -- see 49.2.6.

2 - Most GPIO pins have the options under 'PORT control' 11.14.1, the pull-enable and up/down being the two LSBs.

3 - See above -- also a function of PORT control.

4 - All GPIO pins will be 'input' (Hi-Z) as per the 'reset condition' outlined in 49.2.6.  However, for a complete definition of 'pin state at reset' refer to chapter 10.  10.2.2 lists some 'special' reset-values for some members of Port A PORT control, but more particularly the table in 10.3.1 lists the 'default' operational-mode for every pin on the package.  Most pins default to their 'analog' function -- Alternate '0' --  (except the debug pins, on Port A, as selected by those 'special' PORT control values), as this has the least restriction on external connections.

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michelecanepa
Contributor I

Thank you very much Earl !

The answers to all my questions are definitely in that document.

Best,

Michele

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egoodii
Senior Contributor III

I freely acknowledge that pulling a 'full picture' of functions from these 1000+ page documents can be daunting.  In particular, these Freescale Kinetis manuals suffer from a confusion in that the 'peripheral function' descriptions are 'generic' per the design of that silicon module, but many times you have to correlate info from Chapter 3 (and other places!)  to understand what clocks/options/shortcomings come with a particular 'chip'.

Additionally, they DON'T document any details that are considered 'ARM core', leaving THAT to be culled from www.arm.com.

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