Do i need reset MCG clock when exiting LLS mode

[haizhouli]

Hello all,

I am working on Low power mode on Kinetis K21. Based on page 31 in AN4503, I got this:

If the MCG was in PEE when LLS mode was entered from Run mode, it will exit in PBE mode. Note that any module's clocks sourced from the PLL have been off in LLS. Upon wake-up, the frequency will be changed and therefore baud rates and timer counter time bases will change as well. The PLL is functioning but not engaged.

Does this mean I have to reset MCG again to switch it from PBE to PEE once it exits from LLS mode?  Or I just need wait a little bit for PLL and system will be automatically back to PEE mode?

Thanks!

Haizhou

[Hui_Ma]

Hi HaiZhou

When the MCG in PEE mode enter in LLS mode, it exits in PBE mode.

So, it need software to switch MCG working mode from PBE to PEE again.

K21 120MHz example code provides MCG module driver and includes pbe_pee() function.

More detailed info, please download K21 120MHz example code below:

http://cache.freescale.com/files/32bit/software_tools/TWR-K21F120M_LABTS.zip

Wish it helps.
best regards
Ma Hui

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[haizhouli]

Thanks very much for the help and link. Really appreciate!

[yasuhikokoumoto · Accepted solution]

Hi Haizhou Li,

according to the kinetis_50MHz_sc (Sample Code from Freescale), the procedure which PLL waits for entering PEE mode after waking up from the low power mode is described as following. Therefore the answer is the latter of your candidates.

(1) Check MCG is in PBE mode, if not then error.
  if (!(
         (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) == 0x2) &&
         (!(MCG_S & MCG_S_IREFST_MASK)) &&
         (MCG_S & MCG_S_PLLST_MASK) &&   
          (!(MCG_C2 & MCG_C2_LP_MASK))
  ))  {   return ERROR;   }

(2) Check the PLL state before transitioning to PEE mode, if not then error.
  for (i = 0 ; i < 2000 ; i++)
  {
    if (MCG_S & MCG_S_LOCK0_MASK) break;
  }
  if (!(MCG_S & MCG_S_LOCK0_MASK)) return ERROR;

(3) Clear CLKS to switch CLKS mux to select PLL as MCG_OUT.
  MCG_C1 &= ~MCG_C1_CLKS_MASK;

(4) Wait for clock status bits to update, if not then error.
  for (i = 0 ; i < 2000 ; i++)
  {
    if (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) == 0x3) break;
  }
  if (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3) return ERROR;

I hope it will help you.

Best regards,
Yasuhiko Koumoto.

[yasuhikokoumoto]

Hi  Haizhou Li,

my descriptions are just the pbe_pee function contents. I checked the differences them from the sample code shown by Mr. Mui Ma. As the result it is identical.

Best regards.

Yasuhiko Koumoto.

[haizhouli]

thanks very much!