DMA with PIT problem

[wendersonolivei]

Hi all

I'm having a problem with DMA with PIT triggering. I've tried to config the TPM0 (CH0) timer to trigger the DMA, but it doesn't work; I always have a program break at PE_DEBUGHALT(); .

I was testing that because I want to use DMA to output a waveform at DAC, with a sample rate of the PIT. So, I've tried to do this:

#define SINUS_LENGTH 256  uint16_t Sinus[SINUS_LENGTH] = {         2047U,  2097U,  2147U,  2198U,  2248U,  2298U,  2347U,  2397U,  2446U,  2496U,  2544U,  2593U,  2641U,  2689U,         2737U,  2784U,  2830U,  2877U,  2922U,  2967U,  3012U,  3056U,  3099U,  3142U,  3184U,  3226U,  3266U,  3306U,         3346U,  3384U,  3422U,  3458U,  3494U,  3530U,  3564U,  3597U,  3629U,  3661U,  3691U,  3721U,  3749U,  3776U,         3803U,  3828U,  3852U,  3875U,  3897U,  3918U,  3938U,  3957U,  3974U,  3991U,  4006U,  4020U,  4033U,  4044U,         4055U,  4064U,  4072U,  4079U,  4084U,  4088U,  4092U,  4093U,  4094U,  4093U,  4092U,  4088U,  4084U,  4079U,         4072U,  4064U,  4055U,  4044U,  4033U,  4020U,  4006U,  3991U,  3974U,  3957U,  3938U,  3918U,  3897U,  3875U,         3852U,  3828U,  3803U,  3776U,  3749U,  3721U,  3691U,  3661U,  3629U,  3597U,  3564U,  3530U,  3494U,  3458U,         3422U,  3384U,  3346U,  3306U,  3266U,  3226U,  3184U,  3142U,  3099U,  3056U,  3012U,  2967U,  2922U,  2877U,         2830U,  2784U,  2737U,  2689U,  2641U,  2593U,  2544U,  2496U,  2446U,  2397U,  2347U,  2298U,  2248U,  2198U,         2147U,  2097U,  2047U,  1997U,  1947U,  1896U,  1846U,  1796U,  1747U,  1697U,  1648U,  1598U,  1550U,  1501U,         1453U,  1405U,  1357U,  1310U,  1264U,  1217U,  1172U,  1127U,  1082U,  1038U,  995U,   952U,   910U,   868U,         828U,   788U,   748U,   710U,   672U,   636U,   600U,   564U,   530U,   497U,   465U,   433U,   403U,   373U,         345U,   318U,   291U,   266U,   242U,   219U,   197U,   176U,   156U,   137U,   120U,   103U,   88U,    74U,         61U,    50U,    39U,    30U,    22U,    15U,    10U,    6U,     2U,     1U,     0U,     1U,     2U,     6U,         10U,    15U,    22U,    30U,    39U,    50U,    61U,    74U,    88U,    103U,   120U,   137U,   156U,   176U,         197U,   219U,   242U,   266U,   291U,   318U,   345U,   373U,   403U,   433U,   465U,   497U,   530U,   564U,         600U,   636U,   672U,   710U,   748U,   788U,   828U,   868U,   910U,   952U,   995U,   1038U,  1082U,  1127U,         1172U,  1217U,  1264U,  1310U,  1357U,  1405U,  1453U,  1501U,  1550U,  1598U,  1648U,  1697U,  1747U,  1796U,         1846U,  1896U,  1947U,  1997U };  void InitTimer(void) {   TPM0_SC = 0;    TPM0_CNT = 0;   TPM0_MOD = TPM_MOD_MOD(0xFFFF);   TPM0_C0V = TPM_CnV_VAL(0x1770);    TPM0_C0SC = (TPM_CnSC_CHIE_MASK | TPM_CnSC_MSA_MASK | TPM_CnSC_DMA_MASK);    TPM0_SC = (TPM_SC_CMOD(0x01) | TPM_SC_PS(0x00) | TPM_SC_DMA_MASK); //Set up clock and prescaler }  void InitMuxDMA(void) {   //Channel Configuration Register   DMAMUX0_CHCFG0 = DMAMUX_CHCFG_ENBL_MASK | DMAMUX_CHCFG_TRIG_MASK | DMAMUX_CHCFG_SOURCE(24); }  void InitDMA(void) {   //DMA Source Addr   DMA_SAR0 = (uint32_t)&Sinus[0];   //DMA Destination Addr   DMA_DAR0 = (uint32_t)&DAC0_DAT0L;   //DMA Status Register/ Byte Counter Register   DMA_DSR_BCR0 = DMA_DSR_BCR_BCR(256);   //DMA Control Register   DMA_DCR0 = DMA_DCR_ERQ_MASK | DMA_DCR_CS_MASK | DMA_DCR_SINC_MASK | DMA_DCR_SSIZE(0b10) | DMA_DCR_DINC_MASK | DMA_DCR_DSIZE(0b10);   //DMA Mux   InitMuxDMA(); }

Target: KL25Z

Can anyone help?

Original Attachment has been moved to: DMA-error-project-(FRDM-KL25Z).zip

[wendersonolivei]

BlackNight, I found what causes the unhandled exception. It was happening due a clk config missed. Thanks by the tip for ISR!

The code without exception:

void InitTimer(void)
{
  SIM_SCGC6 |= SIM_SCGC6_TPM0_MASK;
  TPM0_SC = 0;
  TPM0_CNT = 0;
  TPM0_MOD = TPM_MOD_MOD(0xFFFF);
  TPM0_C0V = TPM_CnV_VAL(0x1770);
  TPM0_C0SC = (TPM_CnSC_CHIE_MASK | TPM_CnSC_MSA_MASK | TPM_CnSC_DMA_MASK);
  TPM0_SC = (TPM_SC_CMOD(0x01) | TPM_SC_PS(0x00) | TPM_SC_DMA_MASK); //Set up clock and prescaler
}

void InitMuxDMA(void)
{
  //Channel Configuration Register
  SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
  DMAMUX0_CHCFG0 &= ~DMAMUX_CHCFG_ENBL_MASK;
  DMAMUX0_CHCFG0 |= DMAMUX_CHCFG_TRIG_MASK;
  DMAMUX0_CHCFG0 |= DMAMUX_CHCFG_SOURCE(24);
  DMAMUX0_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK;
}

void InitDMA(void)
{
  //Init DMA Clock
  SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
  //DMA Source Addr
  DMA_SAR0 = (uint32_t)&Sinus[0];
  //DMA Destination Addr
  DMA_DAR0 = (uint32_t)&DAC0_DAT0L;
  //DMA Status Register/ Byte Counter Register
  DMA_DSR_BCR0 = DMA_DSR_BCR_BCR(256);
  //DMA Control Register
  DMA_DCR0 = DMA_DCR_ERQ_MASK | DMA_DCR_CS_MASK | DMA_DCR_SINC_MASK | DMA_DCR_SSIZE(0b10) | DMA_DCR_DINC_MASK | DMA_DCR_DSIZE(0b10);
  //DMA Mux
  InitMuxDMA();
}

But, anyway, the DMA wasn't handled the DAC. Someone knows why?

[BlackNight · Accepted solution]

I have not tried your example (PIT triggered), but I experimented with DMA and PWM. Maybe this helps:

http://mcuoneclipse.com/2014/06/07/tutorial-pwm-with-dma-on-armkinetis/

There is as well

First Adafruit NeoPixel Blinks with the FRDM Board | MCU on Eclipse

and

http://mcuoneclipse.com/2014/07/27/led-clock-with-kitchen-hot-pan-protector/

where I use DMA.

DMA code is in

mcuoneclipse/NeoPixel.c at master · ErichStyger/mcuoneclipse · GitHub

The Processor Expert Init component for DMA has a setting for PIT triggered DMA. When I tried this, I remember that worked as expected. So I think just something is missing in the settings.

[wendersonolivei]

I got that with your DMA and PWM example. Thanks!

[BlackNight]

To know which interrupt was raised, could you enable 'own for every' in the Processor Expert CPU build tab settings?

See Oh my! An Interrupt… | MCU on Eclipse

That way we would know at least what interrupt is firing.

Erich

[wendersonolivei]

Hi Erich!

Thanks, it's really helpful (not only for this project).

Well, now I know that is a Cpu_ivINT_Hard_Fault isr, and this is happening when I try to write the DMAMUX0_CHCFG0. Do you know why a write occurrence on this reg is generating this error?

[BlackNight]

Looks you already identified the spot what caused the hard fault.

Just in case, if not seen these:

http://mcuoneclipse.com/2012/11/24/debugging-hard-faults-on-arm-cortex-m/

and for Processor Expert there is even a dedicated component:

http://mcuoneclipse.com/2012/12/28/a-processor-expert-component-to-help-with-hard-faults/

This helps with debugging hard faults.

Erich