Hi
The ICS in the KE02 is very simple and the best place to start is with the clock distribution block diagram that is found in its user's manual:
There is a practial discussion of the MCG as found in the more powerful K parts at http://www.utasker.com/kinetis/MCG.html, whereby the MCG is still a sort of a super-set of the ICS and so most principles hold true.
In the uTasker project the FRDM-KE02Z settings are simply set by a few defines:
To run at 8MHz from the internal 32 kHz IRC:
#define RUN_FROM_DEFAULT_CLOCK // default mode is FLL Engaged Internal - the 31.25kHz IRC is multiplied by FLL factor of 1024 to obtain 32MHz nominal frequency
#define SYSTEM_CLOCK_DIVIDE 4 // divide the FLL output to give the system clock (maximum 20MHz) (/1, 2, 4, 8, 16, 32, 64 or 128 possible)
#define BUS_CLOCK_DIVIDE 1 // divide by 1 or 2 to give bus and flash clock (maximum 20MHz)
which is verified in the uTasker FRDM-KE02Z simulator as shown below.
If you need to know the exact code it is simply two lines:
| SIM_BUSDIV = 0; | // bus clock is equal to the system clock (ICSOUTCLK) | |
| ICS_C2 = _SYSCLK__DIV; | // set system clock frequency (ICSOUTCLK) once the bus/flash divider has been configured |
where
#define _SYSCLK__DIV (ICS_C2_BDIV_4)
for the 8MHz case, which is controlled by the original setting.
Regards
Mark
See also http://www.utasker.com/kinetis/FRDM-KE02Z.html for a complete solution.
