I am trying to set up the I2S signals with processor expert using the SSI_LDD . I don't seem to be able to get the bit clock and master clock to be in an 8:1 ratio. The master clock seems to always include a divide by 250 in the divider chain and the bit clock does not. I have tried various frequencies but they always have the divide by 250 in the chain. Other ratios are acceptable such as 16:1 and 12:1. In the I2S0_MclkDiv line of the clock path tab of the Master Clock, Clock rate select button there appears to be a 256 divide option but I can't seem to select it.
Hello Tom,
(1) Do you mean this can not change ? ->
These configuration of "Clock path" are calculated after we choose "Clock rate", so it can not change by hand.
(2) How to configure the clock ? first we need configure the CPU clock :
then , refer to your demand calculate the Clock rate of I2S, then choose it on clock rate.
(3) Where is the "bit clock" ?
Have a great day,
Alice
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
If I pick 1.4996 Mhz as the bit clock which is an exact power of 2 down from the 95.997 then the bit clock divides by 2 and then 32. Using 11.997 for the master should be attainable as an exact power of 2 division. PE however chooses to first divide by 250 then x 30 . rather than 256 and 32. This gives 11.517 mhz instead of 11.997.
Hello Tom,
Could you tell me which chip ? And send me your project which have configuration I2S, i will test and calculate on my side .
BR
Alice
I believe I attached a project already. I am using the MK10DN512VLK10. If you try to enter 11.997 for the master clock which is an exact power of 2 down from 95.977 it chooses to divide by 250 instead of 256. I have attached the spec sheet for the codec that I am interfacing to. See the table on page 9. If I try 12.288 for the mclk it chooses to divide by 250 and multiply by 31 to give me 11.901 instead of multiplying by 32 and giving me 12.28512. If I choose 1.536 for the bit clock it chooses 1.6 Mhz when it could have divided by 250 and multiplied by 4 to give me the correct frequency.
Note that the I2S0:Init_I2S component allows the bit clocks to be derived from the mclk giving the precise ratio however I have not been able to get the I2S_PDD to work properly as noted above and in the attached project.
I enquired as to if a non-exact mclk could work here is the reply, which I pretty much expected:
Hi Tom,
MCLK/BICK/LRCK does require exactly their respective power-of-two relationships. Otherwise, internal synchronization will not be correct and the converter will periodically reset itself.
Thanks and regards,
Joel Jones
Applications Engineer
AKM Semiconductor
(408) 436-8580 x5530
1731 Technology Dr., Ste. 500
San Jose, CA 95110
USA
Hi Tom,
Which IDE ? and the version .
Hello ,
I have configure the i2s clock on KDS2.0 , i have not found error .
I'm sorry i really can not understand your problem :
(1) "the bit clock should be 1/8 of 11.901" , what's mean the "1/8" ?
the bit clock :
after we finish the configuration of PE , we can got the code (for example the transmit clock (bit clock ) ) :
you can refer to the reference manual to check the "I2Sx_TCR2" register .
(2) In general, the clock data is close to the data which configure form the register ,there have the "Allowed error" .
And if you really want one clock , while the PE have not , you can change the register by hand in the "SSI1.C" file .
BR
Alice
The receive clock and the master clock must be in an exact 1:8 ratio. If I set the master clock to 12.288 Mhz then it gives me 11.901 Mhz. It is actually 11.901148 (95.977/250*31). So I must then have a receive clock of 11.901 divided by 8 which would be 1.487625 or more precisely 1.4876435 (11.901148/8). The receive clock generated is 1.500 Mhz (actually 1.499640) which is not 1.487625 or 1.4876435.
An allowed error in frequency is acceptable when interfacing to a codec but the clocks must be in an exact ratio. This exact ratio is achievable in the processor hardware but processor expert does not allow this to be achieved.
Hello Tom,
Sorry i don't know why 1:8 ratio .
While it doesn't matter, if yo want the receive clock is 1.487625 or more precisely 1.4876435 (11.901148/8) , do you know the how to
configure the related register, for example I2S0_RCR2 ? If yes, the workaround is configure the register by hand .
For the receive clock is configure by the registers .
BR
Alice
I have found a work around by not using this component and I now completely understand the registers. It is essential that the ratio be precisely 8:1 as confirmed by the manufacturer of the codec. I sent his reply to this in a previous email. It appears that there is a bug in this component, the software is not generating the correct frequencies when it should be able to.
Yes I have found all of that. If I desire a master clock of 12.288 Mhz it gives me 11.901. For 11.901 then the bit clock should be 1/8 of 11.901 or 1.487625. If I type 1.487625 I get 1.5 Mhz. It is not critical for the frequencies to be any exact number but I think it is important for the bit clock to be 1/8 of the master.