15.3.6 Interrupt Control Register (ICRnx)
Each ICRnx, where x equals 1, 2,..., 63, specifies the interrupt level (1–7) and the priority within the level
(0–7). All ICRnx registers can be read, but only ICRn8 to ICRn63 can be written. It is the responsibility
of the software to program the ICRnx registers with unique and non-overlapping level and priority
definitions. Failure to program the ICRnx registers in this manner can result in undefined behavior. If a
specific interrupt request is completely unused, the ICRnx value can remain in its reset (and disabled) state
I agree. I call it "EMG considered harmful". The UART code included some support for different logical numbers vs. physical uart numbers, but that was broken when I tried to use it. The heap allocation stuff works but the statistics and debugging code with it is broken. There's a nasty bug in printf where they expand LF to CRLF in some cases but not in others; this will screw you up if you are using sprintf to build a multi-line web response where you need just 1 CR before the LF. I ended up discarding the entire EMG webserver and built a complete replacement.I'd have to say I'm not too pleased with the quality of the DEMO code. Too many 'fixes' and other mods look to have been made to push the demo out the door. Flip what you would think is a simple alternative implementation via a #define and you have to fight your way thru the code to see why it now doesn't work. UART is a good example of that. Other code commented out with no explanation and other places questionable crumbs look to have been left.