MCF51QE Clocking Questions

[RRRitchey]

Hi,
I am new to Freescale, used MSP430, but am switching my entire product line over.  I am just getting started on the MCF51QE family on a new design.  I am a bit confused about the best way to configure the ICS.  I need to run my timers at 4MHz.  I would like to run the CPU at the highest rate possible.  I need an accurate clock so I am going to run an external resonator.   One thing that I miss, unless I am wrong, is the oscillator failsafe mode of the MSP430.  I see no provision in the MCF51QE to failsafe to the DCO if the external oscillator quits.  Did I miss anything?  It seems that if I use a 4MHz reference resonator (which I already use in quantity) I will need to run the CPU at 32MHz in order to be able to divide this down for the timers to run at 4MHz since there are only binary prescalers for the timers.  Thanks for any feedback on these issues.

[jreyes085]

Please Ritchey, i hope you got a solution for this problem, can you help me dealing with this?

thanks...

[RRRitchey]

Hi,

I basically had to run the CPU at 32MHz which gave me a bus clock of 16MHz.  I then had to use the divider on the timer to divide this by 4 to give me my 4MHz.  There is no way to to use arbitrary dividers for the timers.  If you need a specific timer sample rate then you have to work backwards to see what the maximum you can run the CPU at is. 

[jreyes085]

Im using the demoqe128 board.

The board has a crystal of 62768 Hz as a external oscillator. I want the Bus clock (BUSCLK) to be at least 4MHz (I want the BUSCLk to be 4MHz), that would require a ISCOUT of 8MHz.
 
The problem is that im confused about configuring the ICSC1, ICSC2, ICSTRM,ICSSC, NVFTRIM & NVICSTRM registers. I made this config of these register:

ICSC1= 00 000 0 0 0 ;

CLKS (00): I chose the DCOOUT to be later divided by 4,

RDIV (000): Divided by 1,

IREFS (0): chose external ref,

IRCLKEN (0): Disables Internal ref,

IREFSTEN (0): Disables Int ref in stop mode.

ICSC2= 10 0 1 0 1 1 1 ;

BDIV (10): Divides DCOout BY 4,

RANGE(0): low freq range for the external oscillator,

HGO(1):  High gain operation,

LP(0): FLL is not disabled im byass mode,

EREFS(1): Oscillator requested,

ERCLKEN (1): ICSERCLK active,

EREFSTEN(1): External reference clock stays enabled in stop

ICSSC= 01 0 0 00 1 0 ;

DRS(01): DCO Mid range,

DMX32(0):  DCO has default range of 25%,

IREFST(0) Read-only: Source of refence clock is external clock,

CLKST (00) Read only: Ouput FLL is selected,

OSCINIT(1) Read only: If EREFS is set and the external reference clock is selected by ERCLKEN or by ICS being in FEE, FBE, or FBELP, this bit is set after initialization cycles of the external oscillator clock have completed. This bit only cleared when either ERCLKEN or EREFS are cleared,

FTRIM(1):ICS fine trim, setting FTRIM increases the period.

* I want to to this using the external oscillator as the reference clock. It has two Capacitors of 2pF, feedback resistor of 1Mohm in the schematic (but i measured directly on the board and it is of 35Mohms), and a series resistor of 4ohms.

I haven't run it in code warrior but i have my doubts about if it will work.

I post an image in this message, i want a ISCOUT of 8 MHz using the FLL and the external oscillator of the demo board.  The DCOOUT must be of 32Mhz, and i dont know if this configuration is correct. I have my doubts about the DRS and DMX registers, what i did is it wrong? and the FTRIM register, im not using the internal ref, what do i do?

 Is this the way you did it?

Ok, thanks...

[jreyes085]

Im confused too. That's right, i might run the cpu at 32MHz to be able to have a BUS CLOCK of 4MHz after dividing in two, and then again dividing in two. That's a good config option???

I know this post is too old and no one answered this,  anyway im posting over here, but im making a new post to ensure that somebody answers me.

Thankssss!