Debugging ethernet PHY

[ElioMussini]

Hi, we have been trying for last few days to debug an ethernet link problem with a design based on the 52259 EVB.

Our design is using the same transceiver, magnetics and MII interface as seen in the EVB schematics, and of course the same PHY transceiver (DP83640).

The 52259 in our design can be flashed with no problems, and runs fine. We are testing with CW72 and the MQX3.5+RTCS stationary, but unfortunately we can not establish ethernet link between our design and the network.

The RTCS inits the 83640 part without any errors reporting, and it can bind to a static IP address with no problems, but our design wont reply to a ping from a different host, and of course our status leds are not showing ethernet link.

Looking at the DP83640 Datasheet, section11.4.5, Normal Link Pulse Detection/Generation, for 10BaseT in absence of link, the PHY is expected to send/look for 100ns pulses transmitted every 16ms.

The odd part is that our design is sending 16ms/50ns pulses instead. 

We think the problem is related to the pulse width, but not sure. As hard as we are trying, we are unable to identify the link problem, any ideas wolud be greately appreciated

Elio Mussini

[DavidS]

Hi Elio,

I think there was bug in the PHY code for 3.5 that was fixed in 3.5.1 update for the M52259EVB Ethernet PHY.

I just cannot find the exact reference.

Regards,

David

[ElioMussini]

David, thanks for your feedback. Unfortunately I tried 3.5.1and still no link. Any other Ideas would be appreciated.

Elio

[DavidS]

Hi Elio,

Only suggestions that come to mind are to:

- review schematics

- write code to verify you can read/write to the PHY (is the PHY address coded correctly?)

- does connecting to a switch or router change behaviour?

Regards,

David

[ElioMussini]

Hi David, thanks for the follow up. Still not resolved the issue. As you suggested, we wrote a program to read/write the PHY registers, and it worked fine, meaning we can access the part through the MII interface. We also checked schematics and now we are building another prototype to rule out any possible hardware problems.

Something we also tried is changing the TCP/IP stack, we used MQX 3.5, 3.5.1, uTasker and now FNET 0.7.1.

We also ordered a 52259EVB to compare with our design. Ill keep you posted. Thanks again

Elio

[ElioMussini]

Hi David, just to let you know that we received the 52259EVB, tested the Ethernet interface. Of course, we found no problems, but unfortunately we still can't make our design work.

We compared all registers and straps between our board and the EVB, but found not difference.

The only big difference is the TX_CLK: in our board is 50Mhz instead of 25. When switch our board to 10BaseT , TX_CLK frequency is again wrong: 5mhz instead of 2.5.Mhz

We don't understand why the TX_CLK is internally generated in the 83640 and not derived from the 25Mhz crystal. We also verified that the PHY is in MII mode by reading the RBR register (0x17).

Thanks again, any suggestions are highly appreciated

Elio Mussini

[tamirci]

Hi Elio and David,

We are also expriencing the same problem with the same PHY. Did you clear this issue or any solution?

Best regards,

[DavidS]

Hi Serkan,

I haven't heard if resolved or not.  Elio?

It sounds like the PHY was configured for RMII MAster mode if it provided the clock and the clock was 2x what the MII mode would have it....but Elio indicated that they read the PHY register to say it was in MII mode. 

Regards,

David

[tamirci]

Yes David,

I m living the same thing like Elio. I m reading PHY registers and it says configured as MII 100Mbps. So i m expecting 25Mhz TX_CLK but i m seeing 56Mhz. Furthermore i m configuring it as 10Mbps and i m seeing 5 Mhz TX_CLK instead of 2,5 Mhz. I m testing the same codes with MCF52259EVB and i m getting correct results; 25Mhz TX_CLK for 100 Mbps, 2,5Mhz TX_CLK for 10Mbps.

This issue broke our project at the final stage and we need to clear issue as soon as possible. I e-mailed to national semiconductor but no answer from them.

Best regards,

[DavidS · Accepted solution]

Hi ALL,

Two customers experienced the same Ethernet PHY configuration issue causing clocks to be incorrect.

The problem was incorrect resistor value.

The problem ended up being the wrong resistor value used for the DP8340 Vref to ground.  It should be 4.87k 1% resistor.  Once correct resistor replaced the systems worked properly.

Regards,

David