Can anyone out there help me with a MC68336 QADC issue?

[michaelklos]

I am trying to use a debugger to poke values into the registers to get the QADC to do a single pass reading the ADC values.  I'm confident I have the CCW registers setup properly.  I just cannot get it to kick off a single pass software scan.

[TomE]

It would help if you detailed how you are setting the QADC up and what values you are writing to what register addresses.

Have you got the STOP and FRZ bits clear?

Have you set up all of the QADC Control registers? Have you read them back to make sure your writes are working? What is showing up in the STATUS register after your attempted commands?

It is possible the registers only respond to WORD writes, and your debugger is doing everything as BYTE writes. That is a common problem.

Tom

[michaelklos]

Thank you for looking at this.

First, I believe the debugger is doing word writes.  Any attempt to do a pokew to an odd address causes a fault.  I would not expect that if it were doing byte writes.

I setup the QADC as follows:

Initialize the QADC Module Configuration Register, and QADC Prescale Register.

1. a)      (FFF200) = 0000

            Set QADC64 mcr for normal operation (should be default)

1. b)      (FFF20A) = 0033

      Set QACR0 to have a high prescale of 4 & low prescale of 4. PSH = 3 PSL = 3.

      Internally muxed. (Non Muxed externally)

1. c)      (FFF20E) = 0040

Set QACR2 to disable Queue2, and only run queue 1. Note, this should be the default value.

Initialize the Command Conversion Words (CCW), No Bypass (BYP), No Pause (P), Input Sample Time QCLK Period x 16

1. a) (FFF230) = 00F4            Analog A0 = AN52
2. b) (FFF232) = 00F5            Analog A1 = AN53
3. c) (FFF234) = 00F6            Analog A2 = AN54
4. d) (FFF236) = 00F7            Analog A3 = AN55
5. e) (FFF238) = 00F8            Analog A4 = AN56
6. f) (FFF23A) = 00F9            Analog A5 = AN57
7. g) (FFF23C) = 00FA            Analog A6 = AN58
8. h) (FFF23E) = 00FB            Analog A7 = AN59
9. i) (FFF240) = 00C0            Analog B0 = AN0
10. j) (FFF242) = 00C1            Analog B1 = AN1
11. k) (FFF244) = 00C2            Analog B2 = AN2
12. l) (FFF246) = 00C3            Analog B3 = AN3
13. m) (FFF248) = 00F0            Analog B4 = AN48
14. n) (FFF24A) = 00F1            Analog B5 = AN49

• o) (FFF24C) = 00F2            Analog B6 = AN50

1. p) (FFF24E) = 00F3            Analog B7 = AN51
2. q) (FFF250) = 00FC            Analog Vrl
3. r) (FFF252) = 00FD            Analog Vrh
4. s) (FFF252) = 00FE            Analog (Vrh-Vrl)/2
5. t) (FFF252) = 00FF            End of Queue (EOQ)
   
   

Set QACR1 for a single scan

(FFF20C) = 2100

That is my process.  I scripted it so I can repeat it.  Before and after writing to QACR1 I check the result registers and they have not changed.  If I zero result registers, then try to get a scan, they do not change.  Therefore I'm assuming the QADC is not running a scan.

Thank you,
Michael

[TomE · Accepted solution]

Complicated piece of kit, isn't it? At least it is well documented, unlike the modern extremely complicated kit in newer CPUs.

> c)      (FFF20E) = 0040

> Set QACR2 to disable Queue2, and only run queue 1. Note, this should be the default value.

According to my manual, the default value is 0027 and the 0040 bit in that register is "not used". It looks to me like you've set the queue start to ZERO. "8.12.7 Conversion Command Word Table" says to set BQ2 to "a value greater than 39" to disable the queue, which would be 40 or 0x28. So the documented default of 0x27 is just weird...

You're meant to set it to "40 DECIMAL". You've set it to "40 HEX"!

The command table looks OK.

The command looks OK, but I'd suggest 0x2500 to see if you can get it continuously scanning. Then look at CS and CWP in the Status register.

I wouldn't assume zero in the result registers means it didn't run. The conversions may have turned out to be zero. One or more of the reference voltages may be wrong (the ADC analog hardware may not be powered) so it may be giving that result.

It should be setting the CF1 bit in QASR if it runs.

> If I zero result registers,

How about writing other patterns?

There may still be some interaction with the debug mode that may stop it from working. I'd suggest loading a small function into memory to initialise and start the QADC and then run it from the debugger.

[michaelklos]

You found the error.  Thank you.  Sometimes looking at the same thing too long and I just can't see what's happening.  If you were to contact me off list, I would like to send you a Thank You.

michael@klos.com

[TomE]

Glad to help. Reading the manuals and working these things out is what I do for fun. That you got it working is its own reward.

I can't see why writing 0x40 to the second queue's control register should stop the first queue from working though. You didn't trigger the second queue. Maybe that "unused" bit isn't unused after all?

Tom

[michaelklos]

Thank you.

Michael