Hi：
Recently, when I used SGMII of MSC8157, I saw a demo in the SmartDSP folder under the CodeWarrior software installation package directory (the path is as follows): SmartDSP\demos\starcore\msc815x\rionet.
I don't know how to modify and use this project to implement the interface function of SGMII I use. The following figure is the wiring diagram of my SGMII:
I hope I can get detailed help instructions, thank you very much.
Hi：
Hi：
Hi xiangjun:
I am already in the testing phase. When I tested the SGMII of MSC8157, my MSC8157 was doing a TCP client. The PC was a TCP server. The client could connect to the server and communicate easily. I encountered a very strange problem during the test. My specific operation is as follows:
After the client connects to the successful server, it will continue to send 1024 bytes of data to the server, but from the speed of receiving data from the server, there is only about 5-9KBytes per second (5 to 9K bytes/second). ), this feeling is very abnormal, the speed of the Gigabit network port should be at least a few megabytes, why is my only a few K bytes? Here is my configuration:
This is os_config.h
/******************************************************************************
Copyright �1995-2003,2004,2005-2012 Freescale Semiconductor Inc.
All Rights Reserved
This is proprietary source code of Freescale Semiconductor Inc., and its use
is subject to the CodeWarrior EULA. The copyright notice above does not
evidence any actual or intended publication of such source code.
*******************************************************************************/
/******************************************************************************
Copyright �1995-2009 Freescale Semiconductor Inc.
All Rights Reserved
This is unpublished proprietary source code of Freescale Semiconductor Inc.
The copyright notice above does not evidence any actual or intended
publication of such source code.
$Date: 2012/11/22 16:27:41 $
$Id: os_config.h,v 1.3 2012/11/22 16:27:41 sw Exp $
$Source: /home/swproj/sw/REPOSITORY/dsp/SmartDSP/demos/starcore/msc815x/AMC_UEC0_net_demo/os_config.h,v $
$Revision: 1.3 $
**************************************************************************//*
@File os_config.h
@Description OS Configuration definitions.
This file was automatically generated using the
SmartDSP OS Configuration Tool.
@Cautions None.
*//***************************************************************************/
#ifndef __OS_CONFIG_H
#define __OS_CONFIG_H
#include "msc815x.h"
#define ON 1
#define OFF 0
#define MSC81XX_SRIO ON
#define MSC81XX_OCN_DMAx ON
/* OS General Configuration **************************************************/
#define OS_HEAP_SIZE 0x8000 /* Heap size */
#define OS_STACK_SIZE 0x4000
#define OS_HEAP_NONCACHEABLE_SIZE 0x4000 /* Local non-cacheable heap, must be power 2 and >= 256 */
#define OS_SHARED_MEM_SIZE 2048 /* Shared Memory Size */
#define OS_L2_CACHE_SIZE ((uint32_t)&_L2_cache_size)
#define OS_LOCAL_HEAP_MNGMNT_SIZE 3000
#if OS_MULTICORE == 1
#define OS_SHARED_HEAP_MNGMNT_SIZE 5000
#endif
#define OS_TICK ON /* Tick Functionality */
#define OS_TICK_PRIORITY OS_SWI_PRIORITY0 /* Tick Priority */
#define OS_TICK_PARAMETER MSC815X_TICK_001MS /* Tick Parameter */
#define OS_CLKIN 100.0 /* (MHz) */
#define OS_SYSTEM_CLOCK OS_CLKIN /* provided for backward compatibility */
#define OS_HW_TIMERS ON /* Hardware Timers */
#define OS_TOTAL_NUM_OF_MEM_PARTS 8 /* Memory Partitions */
#define OS_TOTAL_NUM_OF_FRAME_POOLS 8 /* Frame Pools Number */
#define OS_TOTAL_NUM_OF_SWI 10 /* Software Interrupts Number */
#define OS_TOTAL_NUM_OF_SW_TIMERS 3 /* Software Timers Number */
#define OS_TOTAL_NUM_OF_QUEUES 48 /* Queues Number */
#define OS_TOTAL_NUM_OF_SHARED_QUEUES 10 /* Shared Queues Number */
/* MULTICORE *****************************************************************/
/* OS_MULTICORE should be defined as 0 or 1 by the compiler */
#define OS_MULTICORE_SYNCHRONIZATION ON /* Multi Core Synchronization */
#define OS_TOTAL_NUM_OF_INTERCORE_MESSAGES 1 /* Intercore Messages Number */
#define OS_NUM_OF_CORES 1 /* Cores Number */
#define OS_MAX_NUM_OF_CORES MSC815X_MAX_NUM_OF_CORES /* Max Cores Number */
#define OS_MASTER_CORE 0 /* Master Core ID */
/* Kernel Awareness************************************************************/
#define USER_KERNEL_AWARENESS_STACK OFF /* User provided kernel awareness stack */
#define KERNEL_AWARENESS_ADDR &osKernelAwareness_b /* User provided kernel awareness base */
#define KERNEL_AWARENESS_STACK_SIZE (uint32_t)&osKernelAwareness_size /*User provided kernel awareness size */
/* Architecture Configuration ************************************************/
#define MSC815X_QBUS MSC815X_QBUS_DEFAULT
#define MSC815X_SYS_REGS MSC815X_SYS_REGS_DEFAULT
#define MSC815X_QE MSC815X_QE_DEFAULT /* For PPC: 0xE0100000 */
#define MAX_NUM_OF_DATA_CONTEXTS 10
#define MAX_NUM_OF_PROG_CONTEXTS 10
#define DCACHE_ENABLE ON
#define ICACHE_ENABLE ON
#define L2CACHE_ENABLE ON
#define OS_PRAM_MEM_BASE (MSC815X_QE + 0x10000) /* For PPC: 0xE0110000 */ /* Parameter RAM Memory base address */
#define OS_PRAM_MEM_SIZE 0xC000 /* Parameter RAM Memory Size */
//#define MSC815X_DMA OFF
/* CIO Devices ***************************************************************/
#define MSC815X_SPI OFF
#define MSC815X_UART OFF
/* BIO Devices ***************************************************************/
#define MSC815X_UEC0 ON
#define MSC815X_UEC1 OFF
#define MSC815X_RIONET0 OFF
#define MSC815X_RIONET1 OFF
#define MSC815X_ATM OFF
/* SIO Devices ***************************************************************/
#define MSC815X_SRIO ON
#define MSC815X_OCN_DMA0 ON
#define MSC815X_OCN_DMA1 ON
/* TASK **********************************************************************/
#define OS_TOTAL_NUM_OF_TASKS 31
//#define MSC815X_TDM0 OFF
//#define MSC815X_TDM1 OFF
//#define MSC815X_TDM2 OFF
//#define MSC815X_TDM3 OFF
//#define MSC815X_TDM4 OFF
//#define MSC815X_TDM5 OFF
//#define MSC815X_TDM6 OFF
//#define MSC815X_TDM7 OFF
/* Total number of devices */
#define OS_TOTAL_NUM_OF_CIO_DEVICES 0//(MSC815X_SPI + MSC815X_UART)
#define OS_TOTAL_NUM_OF_BIO_DEVICES (MSC815X_UEC0 + MSC815X_UEC1 + MSC815X_RIONET0 + MSC815X_RIONET1 + MSC815X_ATM)
#define OS_TOTAL_NUM_OF_SIO_DEVICES 0//(MSC815X_TDM0 + MSC815X_TDM1 + MSC815X_TDM2 + MSC815X_TDM3 + MSC815X_TDM4 + MSC815X_TDM5 + MSC815X_TDM6 + MSC815X_TDM7)
#define OS_TOTAL_NUM_OF_COP_DEVICES 0//(MSC815X_SEC + MAPLE + MAPLE_TVPE + MAPLE_FFTPE + MAPLE_DFTPE)
#endif // __OS_CONFIG_H
//===========================================================//
// This is my App（I omitted a part of the TCPIP initialization screenshot）
//===========================================================//
My configuration on Core in os_config.h is as follows:
Then I performed multi-core simulation and run, observing the information printed by the serial port. From the point of view of the printed information, now 6 Cores are running. Can I understand this?
Multi-core simulation and synchronization I found a manual, according to the manual, it seems to be ok, but when the multi-core is running, it will enter the osHwiDMMUError error.
What is going on with this?
This is my new multi-core configuration.
Hi:xiangjun
I have solved this problem, and now I can communicate with the network normally.
I would like to ask, why when the multi-core is turned on, there will be a problem that the program has been waiting for multi-core synchronization , the program can't go on, single-core debugging is no problem, multi-core debugging will not work.
Hi, HaiFeng,
If it’s multi core project, you need to download and run multi cores .
Or, try the Core0 target and undefining OS_MULTICORE
Hope it can help you
BR
Xiangjun Rong
hi,xiangjun:
I tested the demo at the beginning of net_, but it will die in the void osHwiDMMUError(os_hwi_arg arg) function, always waiting for osWaitForAllCores(); this function does not pass. My interface is SGMII.
