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- CW 4.5 and PE 2.96 -> Problems with XGATE and access to paged external RAM
CW 4.5 and PE 2.96 -> Problems with XGATE and access to paged external RAM
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SOLVED
04-02-2007
11:06 AM
1,843 Views
Ral_Virutas
Contributor I
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Hello¡¡¡ I was working with XGATE a few weeks ago and now I'm working on it again.
I created a project with XGATE using CW Wizard and added a cpu bean with PE 2.96. It requires a few modifications in project but finally it works propperly.
Now we are adding a external RAM support:
We access to an external RAM using RPAGE register. This code has been proved in other projects and works fine, but in this project execution fails when trying to use RPAGE so we are thinking XGATE is interferrring in some way.
¿¿What do you think about that??¿¿Is somebody using RPAGE in a project with XGATE???
Thanks in advance and sorry for my english¡¡¡
I created a project with XGATE using CW Wizard and added a cpu bean with PE 2.96. It requires a few modifications in project but finally it works propperly.
Now we are adding a external RAM support:
We access to an external RAM using RPAGE register. This code has been proved in other projects and works fine, but in this project execution fails when trying to use RPAGE so we are thinking XGATE is interferrring in some way.
¿¿What do you think about that??¿¿Is somebody using RPAGE in a project with XGATE???
Thanks in advance and sorry for my english¡¡¡
Solved! Go to Solution.
1 Solution
04-02-2007
05:10 PM
621 Views
Alban
Senior Contributor II
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Yes indeed and I also explained there why it was not possible...
But as we repeat, I'll put the answer here as well.
Thread has progressed on Yahoo!, that would qualify as crossposting, wouldn't it ?
Hi,
I think I see where the confusion is coming from.
The RAM used on the chip is the same RAM for both XGATE and CPU12X. On the S12XDP512, the XGATE is able to address the full 32KB of RAM of the chip. It is in its 16-bit map without using any paging scheme.
This RAM is also used by the CPU12X. However, the logical=local=CPU memory map only reserved 12KB for RAM (4KB paged and 8KB unpaged) in the 16-bit addressing.
Therefore, the CPU needs the paging to replace the 4KB with appropriate page to be able to access the 32KB.
The XGATE does not support paging. You can look at the datasheet and the instruction set of this RISC co-processor. Everything is 16-bit, opcode is also fixed at 16-bit.
I have no doubt as I use the product daily. (and also teach how to use it).
Cheers,
Alban.
I think I see where the confusion is coming from.
The RAM used on the chip is the same RAM for both XGATE and CPU12X. On the S12XDP512, the XGATE is able to address the full 32KB of RAM of the chip. It is in its 16-bit map without using any paging scheme.
This RAM is also used by the CPU12X. However, the logical=local=CPU memory map only reserved 12KB for RAM (4KB paged and 8KB unpaged) in the 16-bit addressing.
Therefore, the CPU needs the paging to replace the 4KB with appropriate page to be able to access the 32KB.
The XGATE does not support paging. You can look at the datasheet and the instruction set of this RISC co-processor. Everything is 16-bit, opcode is also fixed at 16-bit.
I have no doubt as I use the product daily. (and also teach how to use it).
Cheers,
Alban.
Message Edited by Alban on 2007-04-02 06:19 PM
2 Replies
04-02-2007
03:14 PM
621 Views
CompilerGuru
NXP Employee
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I think you did already ask this question through the yahoo lists, and the answer here is no too.
The XGATE is capable of writing to RPAGE, but doing so has no purpose. So unless you did intentionally (or accidentally) write to RPAGE on our own, the XGATE wont touch it.
Daniel
The XGATE is capable of writing to RPAGE, but doing so has no purpose. So unless you did intentionally (or accidentally) write to RPAGE on our own, the XGATE wont touch it.
Daniel
Reply
04-02-2007
05:10 PM
622 Views
Alban
Senior Contributor II
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Yes indeed and I also explained there why it was not possible...
But as we repeat, I'll put the answer here as well.
Thread has progressed on Yahoo!, that would qualify as crossposting, wouldn't it ?
Hi,
I think I see where the confusion is coming from.
The RAM used on the chip is the same RAM for both XGATE and CPU12X. On the S12XDP512, the XGATE is able to address the full 32KB of RAM of the chip. It is in its 16-bit map without using any paging scheme.
This RAM is also used by the CPU12X. However, the logical=local=CPU memory map only reserved 12KB for RAM (4KB paged and 8KB unpaged) in the 16-bit addressing.
Therefore, the CPU needs the paging to replace the 4KB with appropriate page to be able to access the 32KB.
The XGATE does not support paging. You can look at the datasheet and the instruction set of this RISC co-processor. Everything is 16-bit, opcode is also fixed at 16-bit.
I have no doubt as I use the product daily. (and also teach how to use it).
Cheers,
Alban.
I think I see where the confusion is coming from.
The RAM used on the chip is the same RAM for both XGATE and CPU12X. On the S12XDP512, the XGATE is able to address the full 32KB of RAM of the chip. It is in its 16-bit map without using any paging scheme.
This RAM is also used by the CPU12X. However, the logical=local=CPU memory map only reserved 12KB for RAM (4KB paged and 8KB unpaged) in the 16-bit addressing.
Therefore, the CPU needs the paging to replace the 4KB with appropriate page to be able to access the 32KB.
The XGATE does not support paging. You can look at the datasheet and the instruction set of this RISC co-processor. Everything is 16-bit, opcode is also fixed at 16-bit.
I have no doubt as I use the product daily. (and also teach how to use it).
Cheers,
Alban.
Message Edited by Alban on 2007-04-02 06:19 PM
