HRESET occured during transactio

[yusufalti4444]

Hello NXP, 

We have a custom board based on T1042 processor. We want to flash new RCW on NOR flash using Code Warrior. We can not use hard coded rcw some attributes differ from RDB.

I had 'HRESET occured during transaction ccs_get_subcore_error' when I execute debugger with RCW Override file for t1042 customized with our own values.

Can I have suggestions about this problem? Could it be about FPGA design or RCW? 

Thanks

[ufedor]

Ensure that JTAG connection is implemented as shown in the AN4825 - T1040 Family Design Checklist, Figure 25. JTAG interface connection.

> We can not use hard coded rcw some attributes differ from RDB.

What exactly do you mean?

Hard-coded RCW is somewhat "universal".

Which jtag chain RCW override file you are using?

Please provide it for inspection.

How the RCW was created?

Have you used QCVS PBL Tool?

[yusufalti4444]

>How the RCW was created?

I used  QCVS PBL tool to create RCW according to our board specifications/recommendations. 

>What exactly do you mean?

>Hard-coded RCW is somewhat "universal".

Can we use Hardcoded RCW even if board have different properties when compared with RDB ? 

I attached my RCW override file. I used hexdump tool to view values of PBL.bin file and replaced values of RCW override file with PBL.bin file.

[ufedor]

> Can we use Hardcoded RCW even if board have different properties when compared with RDB ? 

Yes, please try.

[yusufalti4444]

Hello ufedor‌, we are still having same problem with Hard-Coded RCW.

[ufedor]

What are measured frequencies of all clocks applied to the processor?

Please provide corresponding PBL.bin.

[yusufalti4444]

Hello,

I attached the required files.

Our design team have few questions.

1-) What happens if we apply 2.5V on 1v8 bank ? Does HRESET error related with this ?

2-) What is the logic behind POR sequence when Code Warrior tab is connected.

3-) How POR sequence should be in Hard Coded state ?

Thanks.

[ufedor]

1) the processor could be irreversibly damaged in this case

2-3) the question is not clear.

JTAG connection has to be implemented as shown in the AN4825 - T1040 Family Design Checklist, Figure 25. JTAG interface connection.

[yusufalti4444]

1) Is there a way to verify if the chip is irreversibly damaged?

2) In other words for second and third questions, what should FPGA do in the hardcoded case? Power-on sequence includes getting RCW values from nor flash however in the hardcoded rcw adjustment we adjust our config pins for hardcoded option (0x9E). What should be the next step for loading and using our rcw values from nor flash? Should the pins are readjusted from FPGA if we haven't put a "dip switch" option on our board? In addition, for a completely blank and new board, is it a must to configure the chip with hardcoded selection(rcw_src = 0x9E)?

[ufedor]

1) restore correct powering and try to bring-up the board. Also it is possible to compare the processor behaviour with another board having the same design

2) FPGA should not be involved in booting process at all.

> is it a must to configure the chip with hardcoded selection

This is not a must,.just an option.

[yusufalti4444]

"2) FPGA should not be involved in booting process at all."

For this answer, we use our FPGA to bypass cop signals to chip's jtag pins (COP <-> FPGA <-> T1042). In addition, we are just sampling the power-on sequencing signal assertions to control activating "systemclk, por inputs etc.." That means we use our FPGA as CPLD in T1042RDB board. Is there a mistake? Do you have any suggestions according this kind of usage? What should our FPGA do when CodeWarrior TAP try to connect and boot T1042?

Moreover, we have JTAG chain connection problem. However all we do is bypassing COP pins. Is there another method of connection?

Thanks in advance. Sorry for interrupting continuously :smileysad:  

[ufedor]

> What should our FPGA do when CodeWarrior TAP try to connect and boot T1042?

Just pass the COP_JTAG signals the same way as shown in the AN4825 - T1040 Family Design Checklist, Figure 25. JTAG interface connection.

> Moreover, we have JTAG chain connection problem.

> However all we do is bypassing COP pins. Is there another method of connection?

There should be no problem if the FPGA logic is implemented as said above.

[yusufalti4444]

Hello ufedor‌,

In AN4825 Documentation, Figure 25 shows that OVDD is the supply voltage and it is required to be 1.8V, but in T1042RDB, that sense pin is made on 3.3V. Why ?

Thanks.

[ufedor]

> in T1042RDB, that sense pin is made on 3.3V.

Which "sense pin"?

[yusufalti4444]

COP_VDD_SENSE pin

[ufedor]

On the T1042D4RDB COP signals are connected to the CPLD, so 3.3V signalling is used.

[yusufalti4444]

Okay we will try Hard Coded rcw.

Do you have any recommendations about HRESET error? Could it be about DDRCLK or SYSCLCK?