Hi,
I hope I am posting in the right forum.
I have seen this issue on many threads. I learned how to pinpoint the offending address and found that it is the UART0 address.
I am using CW10.5 with FRDM-KE02Z board. I can access the GPIO with no issues but as soon as the first instruction on the PE-generated Init_UART0() routine is executed, I get the Hard Fault.
The UART0 registers seem to be initialized properly (I think):
/** UART - Peripheral register structure */
typedef struct UART_MemMap {
uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */
uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */
uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
uint8_t D; /**< UART Data Register, offset: 0x7 */
} volatile *UART_MemMapPtr;
...
/* UART - Register accessors */
#define UART_BDH_REG(base) ((base)->BDH)
...
/* UART - Peripheral instance base addresses */
/** Peripheral UART0 base pointer */
#define UART0_BASE_PTR ((UART_MemMapPtr)0x4006A000u)
...
#define UART0_BDH UART_BDH_REG(UART0_BASE_PTR)
...
The instruction that fails is:
UART0_C2 &= (uint8_t)~(uint8_t)((UART_C2_TE_MASK | UART_C2_RE_MASK));
showing that the faulty address is 0x4006A000 which is the address of the UART0_BDH register.
Is this a bug in CW 10.5?
Thank you
Hi
Check whether the clock has been enabled to the UART before accesses are made to it:
UART0 bit in register SIM_SCGC
Regards
Mark