BRCLR 6,PCB,*
is a conditional delay based on a bit test on PBWC which is the lock bit of the PLL register. It translates in a 3 byte line of code and in an undetermined delay.
I cannot say anything for the delay but the instruction may be replaced by
NOP
NOP
NOP
which is 3 bytes long and takes 3 HC08 clock cycles just making nothing else. I think that this is ok for your simulation. The best approach is anyway to skip this line by a semicolon to make an easy restoration when compiled on the real board:
; BRCLR 6,PCB,*
Encoder
Message Edited by Encoder on
2008-03-12 06:54 PM