Inaccuracy of TRM value/Clock module at a given temperature locked condition HCSAW32

[Denn]

Dear All,

I have checked the below said things in atleast four of the MCUs.The results were same.

The problem is, say some trim value is loaded into ICGTRM( SFR register) from Non Volatile 250kHz location.I check the Busclock value using CRO through MCLK pin which is configured to give Busclk/2 (SMCLK=0x11; ).

Ideally, I should get the frequency of 4 MHz in locked condition.But in practice the MCLK pin o/p is coming around 3.98--4.02 MHz. i.e. around +/- 0.5% deviation in the BUS CLOCK also the busclock is varying in that range(3.98--4.02 MHz) every instant.

During this bus clock variation observation on CRO(at the same room temperature),I saw the values of "LOCK" bit which was set indicating the MCU was in locked condition.Also the DCO Stable bit was set indicating DCO output was stable

Don't you think that in the 'locked' condition / DCO stable condition, the resulting bus clock should be 8 MHz( MCLK=4MHz).Why is the variation of 0.5%.

Is this normal to have the ICG LOCK bit to set even if there is a deviation of 0.5%?

What is the maximum devaition which the ICG module says its in LOCKed condition,beyond which it says its unlocked.

Waiting for your speedy reply,

Best Regards,

Denn.

Message Edited by Denn*** on 2008-04-10 04:02 PM

[allawtterb]

---

Denn*** wrote:

Is this normal to have the ICG LOCK bit to set even if there is a deviation of 0.5%?

---

Yes this is normal, the ICG LOCK bit becomes set when the FLL output is within +/- 1.5% of the target frequency and the the ICG LOLS is set when the FLL output frequency is +/- 3% of the target frequency.  This information can be found in AN3499 on pg. 18.

http://www.freescale.com/files/microcontrollers/doc/app_note/AN3499.pdf?fsrch=1&WT_TYPE=Application Notes&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation

- Brett

Edit: Added back +/- the forum did not like 

Message Edited by allawtterb on 2008-04-10 03:36 PM

[bigmac]

Hello,

There is another way where the jitter of an output signal may be critical for an application.  This is to use a higher frequency external crystal, and then operate in FEE mode to give highest bus frequency.  However, for the TPM module (assumed to be utilized for the critical timing function in output compare mode), select XCLK as the timing source.

This will virtually eliminate the jitter from the critical output, but will maintain a high bus frequency, where normally some jitter is not important.

When FEE mode is used, the long term accuracy of the bus clock will be as good as the external crystal - it is only short term jitter that is introduced by virtue of the FLL operation.

Regards,

Mac

[Encoder]

S08AW series uses ICG to derive their bus clock. For a medium to good precision bus clock, in order of accuracy, you may:

1) Use FFL with the internal trimmed 243kHz oscillator (FEI mode)

2) Use the FLL with an external precision clock or a crystal (FEE mode)

3) Skip the FLL and use only an external precision clock or crystal (FBE mode)

Keep in mind that:

a) the internal 243kHz oscillator is not very precise: it has an basic ±20% error which may be trimmed up to a typical 0.5% by software during programming.

b) FLL is not exact: it has quite an high jitter istantaneously moving up and down of the theoretical center frequency (up to 0.2%) and the output frequency is not an exact multiple of the base frequency, but a very near value to that.

This way you may find that

1) FEI adds to the basic low-power/no-cost internal oscillator error performance the slight jitter noise of the FLL. It may be unnoticeable for most processes which do not require high accuracy.

2) FEE is better than FEI but the output frequency is not exact as you may expect and it shows some jitter anyway.

3) FBE is the highest precision mode (the same of the external source or the crystal) but it is limited to 8MHz with a 16MHz crystal, the maximum frequency allowed. To achieve the 20MHz limit you must supply an external 40MHz source.

To have a better accuracy than FLL you would use a PLL but unfortunately S08AW has not this facility: if you need that you could switch to the newer S08DN which has PLL option. Either in this case you may have some jitter but this should be fairly lower than in FLL mode and the bus frequency should be an exact multiple of the base frequency. If you need very high quality clock accuracy and no jitter you has no option other than point 3)

Encoder

[fabio]

Hi Denn,

Just in case: how precise is your CRO ? Have you tried measuring a 4MHz oscillator? For such oscillator your CRO shows a steady frequency?

The DS states a maximum 0.2% of jitter on ICGOUT.

Best regards,


Message Edited by fabio on 2008-04-10 04:18 PM

[bigmac]

Hello Denn,

Also keep in mind that the jitter specification given in the datasheet is measured with a 2 millisecond averaging period, i.e. over a period of 8000 bus cycles in your case.  Using the oscilloscope for measurement, and assuming you are synchronising on one edge of the output waveform, and then observing the variation of the opposite edge, you are likely to be observing the short term peak-to-peak jitter.  The peak jitter will be one-half this amount, and there is no averaging occurring.

A better test method against the specification, would be to use timer output compare mode to generate a square wave output with a half-period of 2 millisecond (250 Hz), and observe the peak jitter for this waveform.

Regards,

Mac

[Denn]

Hello Mac,Hello Fabio,

The CRO I used was both Agilent as well as Le Croy. Both have a very good accuracy also both of them are just few months old.

LeCroy gives the max frequency, min frequency, average and SD and so on...

If I see the max frequency, its 4.02--4.03MHz,

Min Freq = 3.97--3.98 MHz

Average Freq most of the time is 4MHz.

Here I see MCU comes under the "maximum 0.2% of jitter on ICGOUT" as the DS states.

What could be the reason for this jitter (+/- 0.5% one bus cycle to another) .Is it the characteristics of ICG Module -FLL? Why isn't the bus cycle period constant?

Regards,

Denn

[bigmac]

Hello Denn,

---

Denn*** wrote:

What could be the reason for this jitter (+/- 0.5% one bus cycle to another) .Is it the characteristics of ICG Module -FLL? Why isn't the bus cycle period constant?

---

Consider that the DCO has a frequency range of 8 - 40 MHz, but the frequency is controlled by 12-bit filter value, in incremental steps.  This means that it is quite unlikely for the DCO frequency to be the required exact multiple of the reference frequency, but will mostly toggle between two different filter values to provide the correct "average" frequency.  This is how the jitter is introduced into the DCO output.

For FEE mode, depending on the reference frequency used, the period over which the presence of frequency error is determined (by counting DCO cycles), and hence the DCO frequency update rate, may vary between about 13 - 64 microseconds.  This will determine the jitter frequency.

For FEI mode, with a trimmed 243 kHz reference, my understanding is that the DCO update will be even less frequent, each 132 microseconds.  This could imply an even larger jitter amplitude.  I note that the jitter specification in the datasheet is applicable to a stable external oscillator configuration.

Regards,

Mac

[fabio]

Hi Denn,

As Mac, Encoder and Brett said, jitter is an undesired component of an FLL circuitry. If your application cannot tolerate such levels of jitter you can:
1 - switch to an external crystal clock source and use FBE mode;
2 - switch to an external crystal clock source, use FEE mode to achieve a higher BUSCLK and use XCLK as the clock source for the TPMs (only TPMs can be sourced by XCLK);
3 - switch to a Dx device, their MCG clock system include a PLL circuitry which provides a much stable output frequency.

Best regards,

[Denn]

Hello Fabio,

Thank you for the feedback.I asked this question out of curiosity.Anyway my application doesn't get affected due to this.

Best Regards,

Denn.