ESCI arbiter function on MC908QB8 and baud rate detection

[bigmac]

Hello all,

There appears to be ambiguity in the MC908QB8 data sheet.  In section 13.9.1, and with SCIACTL register bit ACLK = 0, it is stated that "Arbiter counter is clocked with the bus clock divided by four."  However, in section 13.9.3, again with ACLK = 0, "The counter is clocked with one half the bus clock."  Obviously one of the sections has to be incorrect, but not sure which one.

I wish to consider using the arbiter function for baud rate detection - I wonder if others have used it for this purpose.  Firstly I need to differentiate between a couple of baud rates, and select a standard rate, based on the receipt of one of a few different incoming characters.  I guess this should be relatively straight forward.

The second part of the problem is probably more complex.  I have perceived limitations with using the internal oscillator of the MCU in conjunction with ESCI usage - the long term frequency stability is probably not quite adequate for continued reliability.  The simplest solution is to use an external crystal.  However, this consumes two I/O pins of a 16-pin device, a heavy penalty in some instances.  If I can automatically adjust the ESCI baud rate to exactly match the incoming baud rate, and do this "on the fly", I may be able to utilise the internal oscillator.  I could adjust either the oscillator trim or the ESCI prescale register to compensate for frequency drift.

I would be interested to hear if others have accomplished baud rate measurement and trimming, and the actual strategy utilised.  There doesn't seem to be very much published information on this topic.

Regards,

Mac

[Blaise34]

Hi,

I have no experience with it yet, just planned to get closer in the near future, but I have found some AN when having a look at 908EY16. AN2575 for example describes ICG trimming and ESCI prescaler baud rate adjustment. Probably You can find some useful tips there.

Regards,

Blaise34

[peg]

Hi Mac,

The GT has an ESCI as well and shows /2 in both places.

The QB doc is 1 year old and the GT 2 years old.

The ESCI section is almost word for word with the QB just looking like a later/improved/added to version.

This leads me to guess that a deliberate attempt was made to change it to /4 but only the obvious location was done and the less obvious one missed.

Although I guess you are looking for a better answer than this....

I also guess you are going to be unlikely to find many experts with this if a glaring error like this has gone un-noticed for so long.

Regards David

[Alban]

Dear guys,

EY16, QB8 ESCI should read:

ACLK = 0: with one quarter of the ESCI Input clock (= Bus or Bus x 4, see CONFIG2_ESCIBSRC)
And for ACLK = 1: with one quarter of the ESCI input clock divided by the ESCI prescaler.

I enclosed a Clock tree.

Cheers,

Alban.

[bigmac]

Thankyou Alban.  The diagram considerably clarifies the situation, and shows how "muddled" is the current datasheet.  The block diagram Fig. 13.2 also confuses the issue.

Regards,

Mac

[bigmac]

Hello all,

A further question concerning the arbiter -

Does anyone know if the counter continues to count (from zero) once the overflow bit AROVFL bit is set?  If it does, this would effectively give a 10-bit counter, and could be very useful for lower baud rates.

An observation re measurement of bit period.  If the ACLK=1 mode (pulse width measurement) is used, for any received character with an odd ASCII value, and assuming the arbiter counter is cleared during the previous receive ISR, the arbiter should measure the period of the start bit.  For the ACLK=0 mode (negative edge to negative edge), the number of bit periods measured will have more variation, depending on the received character, and would always be at least two bit periods, including the start bit - not quite as useful.

However, for tha ACLK=1 mode, the nominal count per bit period will depend on the baud divisor (BD) value, but will be independent of the FD prescaler setting.  Since the nominal count value would be 16*BD (assuming BPD=1), the value of BD should not be less than 4 in order to reduce the baud measurement uncertainty to better than plus/minus 1 percent.

For automatic adjustment to allow for internal oscillator drift, I believe a simple strategy would be to increment or decrement the SCPSC prescale register value, to maintain a measured bit period value of 16*BD.

Regards,

Mac

Message Edited by bigmac on 2006-09-18 03:15 PM