908AP32A COP enable

[byteybird9]

I'm using the 908AP32A. The WD or COP is enabled by setting the COPD bit in config1 to zero (power-on reset state). On a prior design using the HC05 processor this was a write once registor. On the 908AP32A this is not indicated as such, meaning if I have a power surge this bit could toggle to a logic "1" disabling the WD. This appears to be whats happening in a test stress condition. Is this true? I am not writting to this registor, I'm using the power-on state. Is this registor really a write-once (as it should be)? Should I write a zero to this registor? Or is there something that I'm missing?

Any help would be greatly appreciated.

[byteybird9]

Thanks.  I justed relooked at the document, section 3.1.  I also checked my code and I'm setting CONFIG1 = 0 on the first statement in main().  Looks like something else is causing the lockup. 

Another solution is to have an external watchdog monitor assert a reset if an I/O pin on the HC08 does not toggle at least once per second.  A problem with this is that during the P&E programming the external WD would force a reset.

[rocco]

Yes, both the CONFIG1 and CONFIG2 registers are write-once. From the data sheet:

"NOTE
The CONFIG registers are not in the FLASH memory but are special
registers containing one-time writable latches after each reset."