[6Solox/Freertos]The Patch to fix the LMEM Address for FreeRTOS_BSP_1.0.0_iMX6SX to enable M4 Cache by default

Document created by Yuan Zhao Employee on Jun 16, 2016
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The LMEM Base address is 0xE0082000u rather than 0xE0002000u.So please apply the patch to FreeRTOS_BSP_1.0.0_iMX6SX to enable the M4 cache, or the cache was not be enabled by default.It may have the big impact to your product performance.

 

diff --git a/platform/devices/MCIMX6X/include/MCIMX6X_M4.h
b/platform/devices/MCIMX6X/include/MCIMX6X_M4.h

index 31d6eb2..3b9d240 100644

--- a/platform/devices/MCIMX6X/include/MCIMX6X_M4.h

+++ b/platform/devices/MCIMX6X/include/MCIMX6X_M4.h

@@ -25584,7 +25584,7 @@ typedef struct {

 

/* LMEM - Peripheral instance base addresses */

/** Peripheral LMEM base address */

-#define LMEM_BASE                                (0xE0002000u)

+#define LMEM_BASE                                (0xE0082000u)

/** Peripheral LMEM base pointer */

#define LMEM                                   ((LMEM_Type *)LMEM_BASE)

#define LMEM_BASE_PTR                            (LMEM)

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