P1025/P1016 Clocking Specific FAQs

[#1]

Does P1016/P1025 come with SerDes clocks enabled? Will P1016/P1025 remain in reset if the SERDES is enabled and no SerDes reference clock is available?

Yes, P1016/P1025 comes with SerDes clocks enabled. However, P1016/P1025 doesn't wait for SERDES PLL lock for it to come out of reset.

For P1016/P1025, which jitter spec (tCLK_DJ, tCLK_TJ or tCLK_DJ+tCLK_TJ) should the buffer and oscillator require to meet?

The input jitter at the SD_REF CLK input is specified, Buffer vendor will have to provide jitter at the output in pk-to-pk terms so that it can be compared with the Tj at SD_REF CLK input

What is the relationship between RMS jitter and peak-to-peak jitter in P1016/P1025? How can I calculate the RMS jitter value from our peak-to-peak jitter value (42 ps and 86 ps)?

RMS jitter is only valid for Random (Gaussian distribution) jitter. This rms value is then converted to pk-to-pk value and added to Deterministic jitter (pk-to-pk) for finding the total jitter (in pk-to-pk). For SD_REF CLK, the HW specs state the value for Total jitter (in peak to peak ps) and Deterministic jitter (in peak to peak ps).

rms value for Rj can be referred from PCI Express™ Jitter and BER Revision 1.0.

Converting the rms to pk-to-pk is not going to help here because the buffer datasheet states the additive phase jitter. This is measured by integrating the phase noise over the frequency band of interest. DDR.

“In asynchronous mode, the memory bus clock speed must be less than or equal to the CCB clock rate which in turn must be less than the DDR PLL rate." Is this statement correct for P1025?

No it is not correct. The correct statement is " In asynchronous mode, if the ratio of the DDR data rate to the CCB clock rate is greater than 3 :1 ( i.e. DDR=3:CCB=1 ), than the DDR performance monitor statistic accuracy cannot be guaranteed."