P1010/P1014 DDR Specific FAQs

[#1]

P1010 has only a single pair of MCK signal, while my device has four Chip Select signals. In a scenario connecting a lot of memory devices under four CS, can the single pair of MCK really drive all of memory devices which are connected by fly-by topology on each CS? In case of P1010 (which has only one MCK), is it really practical to connect DDR3 memory devices under all of four CS? Would it be necessary to use "external CLK buffer" in such a case using four CS?

P1010 was designed for low-cost systems, and as such some of the pins seen on other QorIQ devices (CKE2/3, ODT2/3) were removed to save on cost. For a single-rank, fly-by topology, only one CS would be used. If more ranks were needed, this would be addressed with stacked memories (DDR3 devices that take up to four CS signals).

How does one set up the P1010 or P1014 for a 16 bit data bus size?

To set the data bus width, you need to set DDR_SDRAM_CFG[DBW] bits of the register given in section 9.4.1.7, Page-9-20 of P1010RM Rev-B.

Is it allowed to use four chip-selects with P1010? In my understanding, one ODT signal should be used and be controlled per chip-select? However P1010 has two MODT.

P1010 is designed to use only one chip select with discrete DDR3 DRAM. This requires one CS, one ODT, and one CKE with one clock pair. Additional CS/ODT/CKE are designed for using stacked die DDR3 DRAMs. The four CS, two ODT & CKE, are useful if dual or quad stacked die discrete DDR3 DRAM were used.

For the write leveling, does the P1010 use DQ[0,8,16,24] or use all DQ bit to drive status back to the DDR controller?

P1010 DDR controller can support the write leveling status on any of the data bits within the data byte from a JEDEC standard DDR3 SDRAM.