I am trying to use Output Compare to set (and clear) an FTM channel as a square-wave output, synchronized to a direct digital synthesis (DDS) waveform being generated by the same FTM module.
The FTM_MOD determines the update frequency of the 32-bit DDS phase accumulator. On each FTM overflow, the DDSphase accumulator is incremented by the frequency tuning word (FTW). When the phase accumulator is within a single FTW of overflowing, I calculate the FTM Count at which the projected DDS phase is expected to overflow, and set the Output Compare register to this value. (I am using the FTM_SetupOutputCompare() function from the fsl_ftm.c driver module to do so).
Strangely, when I observe the relative timing of the DDS update and the Output Compare "set", they are always separated by some fixed delay, and not by the value I have calculated. This fixed delay occurs regardless of the FTW (i.e. the DDS output frequency). The fixed delay also occurs if I manually set the Output Compare value to some fixed number less than FTM_MOD, instead of using the formula from the above figure. (For concreteness, the measured delay is almost one full FTM_MOD period).
Is there some reason that the Output Compare register would not be updated immediately?