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KV5x cache and linker file

Question asked by Pietro di Castri on Mar 31, 2018
Latest reply on Apr 3, 2018 by Pietro di Castri

Good morning

I am using the TWR-KV58F220M.

I would like to see in order the cache usage and the linker file.

I read the MKV58F1M0xxx24_flash.ld and I see the 

   m_data_3 space not used at all.

   m_data_2 used only for the heap and stack

  m_data for everything.


The URM of the processor does not detail about the initialization of the cache, the Figure 2-1. is presenting the cache area as part of a block, so I suppose the 16KB + 8KB are inside the m_data and should not be used as data holder unless the cache is disabled.

in the Chapter 3 Core Overview there is a summative description of some memory area.

I do not find a clear description of what the different ram spaces are referring to.

So some simple questions are:

  1. Is the m_data area totaly freely usable for data and ram mapped code?
  2. are the m_data2 and m_data3 slower than m_data?
  3. why the linker file does not use the m_data3?
  4. If I want to choice the m_data, assumed faster for critical code and data is is possible?
  5. Should I move the .data and the .bss in the m_data2 or m_data3 for granting more space in the faster m_data?
  6. There are two section in m_data called  .ncache.init and  .ncache... What are they?


I hope I can get some answers..


Thank You