Memory resources used for boot loader for LPC54606

[Jetcitycowboy]

I also have a separate but related question around the internal flash programming. Is the only way to program/erase the internal flash, from the user application code or the IAR flash writer’s monitor code, by calling the IAP (boot rom) flash programming APIs? If so, can you please clarify on the amount of SRAM0 these boot ROM/IAP can use? 41.3.8.2 is troubling. If the internal boot rom/IAP calls require access to the SRAM0 (or other memory/shared resources) then Microsoft needs to have a list of all such usages, for their secondary boot loader. If their application needs to call the IAP APIs then they would need to budget resources accordingly. Thank you.

I noticed I had not identified the technology sector.  Sorry for the dual entry of the same thing.

[Jetcitycowboy]

Thank you.

I have been unsuccessful in locating this information in the datasheet.  Can you Provide some numbers for  the follow?  MS needs typical and worst case numbers for each item.

Flash erase latency for page erase (256 bytes)

Flash erase latency for sector erase (32K bytes)

Flash program latency for 256 byte page

My understanding is that the MCU is unable to XIP from flash during a flash erase/program operation, is this correct?  Is there a way to suspend an active flash erase/program operation to allow XIP to continue, and to resume the flash operation at a later time?

[Hui_Ma]

Hi,

Chapter 11.1 Flash memory shows the typical time for Flash erase time is 100ms.

The flash memory is not accessible during a write or erase operation.

So, LPC5460x is unable to XIP from flash during a falsh erase/program operation.
There is an application note AN11333 about Interrupt handling during IAP calls for LPC product.
More detailed info, please check below link:
https://www.lpcware.com/content/nxpfile/an11333-interrupt-handling-during-iap-calls-lpc177x8x-and-lp...
Wish it helps.

Have a great day,
Ma Hui

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[Jetcitycowboy]

This is on the OM13092 board with the on board debugger and the IAR tool chain. 

[Hui_Ma]

About IAR IDE reserve RAM range for IAP flash programming, customer could redefine the RAM memory size(remove 128 byte from RAM size) at IAR link configure file (ICF file).

Wish it helps.

Have a great day,
Ma Hui

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[carstengroen]

Why should you reserve 128 bytes at the end of the memory for this ??

It says in the UM, 41.3.8.3 that the space used by the IAP routines are used from the users stackspace (so no reason to "reserve" anything in the memory map (for the linker), just make sure the user stack is large enough to encompass the 128 bytes needed of stack space by the IAP functions:

41.3.8.3 RAM used by IAP command handler
Flash programming commands use the user stack space and may use up to 128 bytes
growing downward.

[Hui_Ma]

Hi Carsten,

You are right. The user manual chapter 41.3.8.3 shows the user stack space usage is up to 128bytes.

While in user manual page 1029 with below description:

So, the top portion of SRAM need reserved 32 byte for IAP application, not 128 bytes.

Have a great day,
Ma Hui

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[Hui_Ma]

Hi,

Yes, it need to call the ROM Flash API to do LPC54608 Flash operation.

Customer call the the ROM Flash API from secondary bootloader is IAP command handler.

From the chapter 41.3.8.3, the Flash programming commands use the user stack space and may use up to 128 bytes.

So, please refer below link to reserve RAM for IAP flash programming:

Reserving RAM for IAP Flash Programming | www.LPCware.com 

And customer also could refer below thread for more detailed info about secondary bootloader application:

IAP RAM Requirements? | www.LPCware.com 

Wis it helps.

Have a great day,
Ma Hui

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