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i.MX6DQ OE and OC assert/negate timing in async mode.

Question asked by Satoshi Shimoda on Sep 29, 2015
Latest reply on Sep 29, 2015 by igorpadykov

Hi community,

 

We have a question about i.MX6DQ EIM.

According to the figures in chapter 22.8 of IMX6DQRM Rev.3, OE and OC signal is asserted/negated at the rising edge of EIM CLK in asynchronous mode.

On the other hand, in IMX6DQCEC Rev.4, OE and OC signal is asserted/negated at the falling edge of INT_CLK.

Which is correct?

 

 

Best Regards,

Satoshi Shimoda

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