i.MX6DQ OE and OC assert/negate timing in async mode.

[satoshishimoda]

Hi community,

We have a question about i.MX6DQ EIM.

According to the figures in chapter 22.8 of IMX6DQRM Rev.3, OE and OC signal is asserted/negated at the rising edge of EIM CLK in asynchronous mode.

On the other hand, in IMX6DQCEC Rev.4, OE and OC signal is asserted/negated at the falling edge of INT_CLK.

Which is correct?

Best Regards,

Satoshi Shimoda

[igorpadykov · Accepted solution]

Hi Satoshi

correct is rising edge of EIM CLK, also datasheet pictures show

timing references to rising edge

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------