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K65 ES Part USB1 PHY PLL Not Locking

Question asked by Rob Bolton on Jun 10, 2015
Latest reply on Nov 17, 2015 by Rob Bolton

The USB PHY PLL will not lock on my custom PCA design. We are using PK65FN2M0VMI18 parts, powered at 3.3V. The VREGIN0 and VREGIN1 pins are tied together, and supplied by a bench supply at 5V so we can watch the current consumed. We are using EXTAL0 driven as an oscillator input (as opposed to crystal), driving it with a high quality (less than 1 ps rms jitter) clock generator. Typically this is set to 12 MHz, but we have also tried 16 MHz and 24 MHz. We are following requirements the May 2015 updated reference manual, with exception to using an oscillator instead of a crystal. We did not hook up USB0, so we can't even revert to using that. We have tried various register settings, and we cannot get the USB PHY PLL to lock.

 

It is worth noting that we can monitor the VREGOUT voltage, and we can control it correctly. We also have done an experiment with register settings and current consumption at VREGIN0 and VREGIN1:

1.) USBREGEN register (bit 31 SIM_SOPT1) cleared => 0 uA

2.) USBREGEN register (bit 31 SIM_SOPT1) set => 190 uA

3.) USBREGEN register (bit 1 SIM_SOPT2, PHY PLL Regulator Enable) cleared => 190 uA

4.) USBREGEN register (bit 1 SIM_SOPT2, PHY PLL Regulator Enable) set=> 330 uA

 

We have verified that the clock coming into the chip through EXTAL0 is able to run lines of code, and can be output on the CLKOUT GPIO pin and is the correct frequency.

 

Has anyone ever gotten USB1 working on the ES parts? We are using the example code from the reference manual and have confirmed are register settings are being written correctly.

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