Relocating DMA buffers to non-cacheable RAM with AT_NONCACHEABLE_SECTION()

[JLa63]

I'm a bit confused about configuring the non-cached sections in MCUXpresso example projects for MIMXRT1060-EVKB.
E.g. building the example project evkbmimxrt1060_flexspi_nor_edma_transfer one would expect that the buffer s_nor_program_buffer[] is located into the memory region NCACHE_REGION, as implicated in source file flexspi_nor_edma_transfer.c:

AT_NONCACHEABLE_SECTION_ALIGN(uint8_t s_nor_program_buffer[256], 4); // I changed the buffer global, for visibility in map file

However, looking at map file the buffer is located into the SRAM_DTC region of the memory:

NonCacheable 0x20003480 0x100 ./source/flexspi_nor_edma_transfer.o
0x20003480 s_nor_program_buffer

instead of being in the NCACHE_REGION region (.ld file):

NCACHE_REGION (rwx) : ORIGIN = 0x81e00000, LENGTH = 0x200000 /* 2M bytes (alias RAM5) */

The provided macro in fsl_common_arm.h looks like:

#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
__attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))

and - as I understand this - it actually doesn't name the memory region, but simply makes a new section in the used memory region used by the default.

Introducing my own macro I managed to locate the buffer into the correct region:

#define DMA_BUFFERS_LOCATE(v, alignbytes) __attribute__((section(".noinit.$NCACHE_REGION"))) v __attribute__((aligned(alignbytes)))

shown in map file:

0x81e00000 s_nor_program_buffer

The memory region NCACHE_REGION is the only SRAM area that is definitely set as non-cacheable in the initialization, and to my understanding should be the one used for dma buffers.

My question is: Have I understood something totally wrong here concerning the dma/cache settings?

Revisions used are:

MCUXpresso IDE v11.6.0 [Build 8187] [2022-07-13]

SDK_2.x_MIMXRT1060-EVKB version 2.12.1

Thanx in advance,
Jukka

[embeddman]

By default non-cacheable region is located in DTCM which is non-cached. If you want to create additional non-cacheable region in OCRAM you should follow the guide https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/Using-NonCached-Memory-on-i-MXRT/ta-p/1183369 

[JLa63]

Thanx for the info, it is not too much emphasized in the documentation. Maybe there should be some kind of tips section in some document: put edma buffers in this region, stacks in that region, heavily used buffers in that region and so on.

Interesting thing however in generated function BOARD_ConfigMPU() in board.c is that the MPU attributes for the DTCM memory region is set cacheable, as shown in the code example:

MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);

Which leads the simple coder thinking that the region in question truly is cacheable.

[jackking · Accepted solution]

I seem to remember some of the SDK examples were missing the sections used by the macro:

 

[JLa63]

Thanx, this was very useful tip, maybe NXP should go through their SDK/examples.

And since we are not having external RAM and DTCM is by default non-cached, we can define the sections as below: