RT1021 'Receiver FIFO Underflow Flag' stuck on?

[rshipman]

Hi.

I have noticed that, for the RT1021, the LPUART FIFO[RXUF] flag (Receiver FIFO Underflow Flag) seems to always be set to 1.
I have also noticed that the driver fsl_lpuart.c does not observe it (blocking or non-blocking), although it does allow you to enable the interrupt and read the flag if you wish.

Is this a silicon bug, am I using this flag incorrectly or is there another setting that is required to reset this flag? Note that this flag is set to 1 even after resetting the LPUART peripheral (as well as after writing a 1 to it because it is w1c). E.g after calling LPUART_SoftwareReset() and before reading DATA.

Thanks for your help.

Ronnie

[jeremyzhou · Accepted solution]

Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
I basically confirm the phenomenon you mentioned, in my opinion, it's a bug.
Have a great day,
TIC

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[rshipman]

Many thanks Jeremy.

Perhaps one for the errata document?

[imxrtuser]

Hello rshipman,

I can't tell you anything about the NXP uart driver or resetting the underflow flag but we are using the RT1021 with the following code to check for underflow in an interrupt service routine:

dwStatus = LPUART_GetStatusFlags(USART_BASE);

if((dwStatus & kLPUART_RxFifoUnderflowFlag) != 0)

{

--> Underflow, stop

}

and this never runs into an underflow with one exception:

If I open the debugger view for the lpuart register in EWARM the debugger reads data from fifo. If there is no data this will result in a fifo underflow.

Did you open the debugger view for the lpuart registers while running your code?

Kind regards,

Steve