Hi Jing, thanks for your reply.
My custom board is based on the MIMXRT1064CVL5A mcu. I use the on-chip 24MHz oscillator to directly feed PLL3_PFD0_CLK (bypassing PLL3_PFD0), which I select as FlexSPI source clock with prescaler 8 (FLEXSPI_PODF) in order to get 3 MHz as FLEXSPI_CLK_ROOT. This should be the SCLK clock driving the esternal serial SRAM in SDR mode, right?
I setup my LUT for the serial SRAM. The following is the flexspi_device_config_t structure I use when I call FLEXSPI_SetFlashConfig() driver function (my target is to map the serial SRAM in memory, accessing to it in DSPI mode):
static const flexspi_device_config_t deviceconfig =
{
.flexspiRootClk = 3000000, /*!< FLEXSPI serial root clock (<20 MHz) */
.isSck2Enabled = 0, /*!< FLEXSPI use SCK2. */
.flashSize = SRAM_SIZE, /*!< memory size in KByte. */
.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle, /*!< CS interval unit, 1 or 256 serial root clock cycle. */
.CSInterval = 1, /*!< CS line assert interval, multiply CS interval unit to
get the CS line assert interval cycles (> 25ns) */
.CSHoldTime = 1, /*!< CS line hold time (> 50ns) */
.CSSetupTime = 1, /*!< CS line setup time (> 25ns) */
.dataValidTime = 0, /*!< Data valid time for external device. */
.columnspace = 0, /*!< Column space size. */
.enableWordAddress = 0, /*!< If enable word address.*/
.AWRSeqIndex = SRAM_CMD_LUT_SEQ_IDX_WRITE_DUAL, /*!< Sequence ID for AHB write command. */
.AWRSeqNumber = 1, /*!< Sequence number for AHB write command. */
.ARDSeqIndex = SRAM_CMD_LUT_SEQ_IDX_READ_DUAL, /*!< Sequence ID for AHB read command. */
.ARDSeqNumber = 1, /*!< Sequence number for AHB read command. */
.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle, /*!< AHB write wait unit. */
.AHBWriteWaitInterval = 0, /*!< AHB write wait interval, multiply AHB write interval
unit to get the AHB write wait cycles. */
.enableWriteMask = 0, /*!< Enable/Disable FLEXSPI drive DQS pin as write mask
when writing to external device. */
};Before I initialize FlexSPI with the following flexspi_config_t structure:
/*Set AHB buffer size for reading data through AHB bus. */
config.ahbConfig.enableAHBPrefetch = true;
config.ahbConfig.enableAHBBufferable = true;
config.ahbConfig.enableReadAddressOpt = true;
config.ahbConfig.enableAHBCachable = true;
config.rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally;
FLEXSPI_Init(base, &config);On my board no FlexSPI DQS pin is available (the two possible pins are all used as GPIO):
Then I try to read (in normal SPI mode) the 1-byte SRAM Mode Register with the following function (2-byte SPI transaction: command byte + data byte):
status_t flexspi_sram_get_mode(FLEXSPI_Type *base, uint8_t *mode)
{
uint32_t temp = 0xFFFFFFFFUL;
flexspi_transfer_t flashXfer;
flashXfer.deviceAddress = 0;
flashXfer.port = kFLEXSPI_PortA1;
flashXfer.cmdType = kFLEXSPI_Read;
flashXfer.SeqNumber = 1;
flashXfer.seqIndex = SRAM_CMD_LUT_SEQ_IDX_RDMR;
flashXfer.data = &temp;
flashXfer.dataSize = 1;
status_t status = FLEXSPI_TransferBlocking(base, &flashXfer);
*mode = temp;
/* Do software reset or clear AHB buffer directly. */
#if defined(FSL_FEATURE_SOC_OTFAD_COUNT) && defined(FLEXSPI_AHBCR_CLRAHBRXBUF_MASK) && \
defined(FLEXSPI_AHBCR_CLRAHBTXBUF_MASK)
base->AHBCR |= FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK;
base->AHBCR &= ~(FLEXSPI_AHBCR_CLRAHBRXBUF_MASK | FLEXSPI_AHBCR_CLRAHBTXBUF_MASK);
#else
FLEXSPI_SoftwareReset(base);
#endif
return status;
}I see my function exits with success, but FlexSPI peripheral actives SRAM chip-select (FLEXSPI_A_SS0_B) for about 200 ns and output 16 clock cycles at about 100 MHz. Obviously, what I read is nonsense, because SRAM maximum SPI clock is 20 MHz.
Where does that 100 MHz clock come from? Can you help me to achieve a right SCLK clock frequency?
And the returned real frequency is 90000000 (90 MHz)!
I don't understand how is possible.... The following is my clocks diagram in the clock configuration tool:
Attached are my clock_config source files. I cannot see my PLL3_PFD0_BYPASS setting in these files, in order to bypass PLL3_PFD0 and have PLL3_PFD0_CLK = 24 MHz to be selected with FLEXSPI_SEL mux as FlexSPI source clock (then divided per 8 with FLESPI_PODF).
In my main() function I call BORAD_InitBootClocks(), which should set clocks with that configuration.
/*!
* @brief Main function
*/
int main(void)
{
BOARD_ConfigMPU();
/* Board pin init */
BOARD_InitBootPins();
BOARD_InitBootClocks();
/* Update the core clock */
SystemCoreClockUpdate();
BOARD_InitDebugConsole();
[...]
}
Where am I wrong?
