i.MX RT1062 Pinout for SEMC in SDRAM mode

[gpontis]

My project requires a high bandwidth interconnection to an FPGA. I am going to use the SEMC in SRAM mode to implement it. Specifically, the SEMC would be used in ADMUX ( multiplexed address and data ), SYNC mode for both reads and writes. Figures 24-63 and 24-66 in the reference manual shows bus signals for these cases.

What is not clear in the reference manual are the SEMC pin assignments for the chip select and clock. Section 24.5.3 has a pin mux table for the SEMC with a column for SRAM.

That table lists CS6 on SEMC_ADDR[8], which according to table 9-1 is presented at GPIO_EMC_17. That seems straightforward enough. Is this correct ? Is only one chip select ( CS6 ) possible for SRAM mode ?

Next up is the clock. Table 9-1 lists SEMC_CLK on GPIO_EMC_26, but table 24-5-3 calls for SEMC_CLKX[0] or SEMC_CLKX[1]. Is GPIO_EMC_26 the physical pin where these clocks will be presented ?

Finally, the SEMC Pin Mux table 24-5-3 lists a signal named CRE appearing on SEMC_ADDR[9]. What is this signal ?

Thanks,

George

[Yuri]

Hello,

 Please look at my comments below regarding Your questions.

1.
   It is correct to use the SEMC_ADDR[8] signal as CS6 for the multiplexed
mode.  Also SEMC_CSXs may be used for CS or address bits higher, than A23.

2.
   According to section 24.3 (Signals) of the i.MX RT1060 Reference Manual,
Rev. 0, 08/2018, SEMC_CLK is used for SDRAM interface. Use SEMC_CLKX[0] for SRAM.

3.
   The CRE signal is intended for CellularRam memory, for the Mode
Register Set command.

Regards,

Yuri.

[gpontis]

I cannot find a pin associated with SEMC_CLKX in either the documentation or the pins tool.

[Yuri]

Hello,

   There are some discrepancies in our i.MX RT1060 ReferenceManual:

the signals SEMC_CLKX[0] and SEMC_CLKX[1] also are named SEMC_CLK5

and SEMC_CLK6.

GPIO_SD_B0_02 has SEMC_CLK5 multiplexing option.
GPIO_SD_B0_0 has SEMC_CLK6 multiplexing option.

Regards,

Yuri.